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Em3rgent0rdr (talk | contribs) →Algorithm: calling s(x) to be a "binary" signum function, to distinguish it from the signum function described in signum function which has 3 output levels. |
Em3rgent0rdr (talk | contribs) →Algorithm: move important stuff about circuit inaccuracies here to be right after the algorithm so can clarify that the the algorithm is "ideal". Add how the accuracy of the DAC is important. Shorten wording on the inaccuracies and introduce ENOB. |
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The algorithm's objective for the {{math|''n''<sup>th</sup>}} iteration is to approximately digitize the input voltage to an accuracy of {{frac|1|2<sup>''n''</sup>}} relative to the reference voltage. To show this mathematically, the normalized input voltage is represented as {{math|''x''}} in {{math|[−1, 1]}} by letting {{math|1=''V''<sub>in</sub> = ''xV''<sub>ref</sub>}}. The algorithm starts with an initial approximation of {{math|1=''x''<sub>0</sub> = 0}} and during each iteration {{math|''i''}} produces the following approximation:<blockquote>{{math|''i''<sup>th</sup>}} approximation: {{math|1=''x''<sub>''i''</sub> = ''x''<sub>''i''−1</sub> − {{sfrac|''s''(''x''<sub>''i''−1</sub> − ''x'')|2<sup>''i''</sup>}}}}</blockquote>where {{math|''s''(''x'')}} represents the operation of the comparator mathematically as a binary [[signum function]]:<math display="block"> s(x) :=\begin{cases}
1 & \text{if } x \geq 0, \\
-1 & \text{if } x < 0. \end{cases}</math>It follows using mathematical induction that the approximation of the {{math|''n''<sup>th</sup>}} iteration ideally has a bounded accuracy of: {{math|{{!}}''x''<sub>''n''</sub> − ''x''{{!}} ≤ {{sfrac|1|2<sup>''n''</sup>}}}}.
When implemented as a real analog circuit, circuit inaccuracies and [[Noise (electronics)|noise]] may cause the binary search algorithm to incorrectly remove values it believes {{math|''V''<sub>in</sub>}} cannot be, so a successive-approximation ADC might not output the closest value. It is very important for the DAC to accurately produce all {{math|2<sup>''n''</sup>}} analog values for comparison against the unknown {{math|''V''<sub>in</sub>}} in order to produce a best match estimate. The maximal error can easily exceed several LSBs, especially as the error between the actual and ideal {{math|2<sup>''n''</sup>}} becomes large. Manufacturers may characterize the accuracy using an [[effective number of bits]] (ENOB) smaller than the actual number of output bits.[[File:ADC animation 20.gif|thumb|alt=Successive approximation animation|Operation of successive-approximation ADC as input voltage falls from 5 to 0 V. Iterations on the ''x'' axis. Approximation value on the ''y'' axis.|right]]
===Examples===
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# The capacitors are then switched so that this charge is applied across the comparator input, creating a comparator input voltage equal to {{math|−''V''<sub>in</sub>}}.
# The actual conversion process proceeds. First, the MSB capacitor is switched to {{math|''V''<sub>ref</sub>}}, which corresponds to the full-scale range of the ADC. Due to the binary-weighting of the array, the MSB capacitor forms a 1:1 charge divider with the rest of the array. Thus, the input voltage to the comparator is now {{math|−''V''<sub>in</sub> + {{frac|''V''<sub>ref</sub>|2}} }}. Subsequently, if {{math|''V''<sub>in</sub>}} is greater than {{frac|''V''<sub>ref</sub>|2}}, then the comparator outputs a digital 1 as the MSB, otherwise it outputs a digital 0 as the MSB. Each capacitor is tested in the same manner until the comparator input voltage converges to the offset voltage, or at least as close as possible given the resolution of the DAC.
▲=== Use with non-ideal analog circuits ===
== See also ==
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