Domain-specific architecture: Difference between revisions

Revision as of 13:04, 3 January 2025

Revision as of 13:05, 3 January 2025

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=== TPU ===

{{See also|Tensor Processing Unit}}

Google's [[Tensor Processing Unit|TPU]] was developed in 2015 to accelerate DNN inference since the company projected that the use of voice search would require to double the computational resources allocated at the time for neural network inference.<ref>{{Cite book |last1=Hennessy |first1=John L. |title=Computer architecture: a quantitative approach |last2=Patterson |first2=David A. |date=2019 |publisher=Morgan Kaufmann Publishers, an imprint of Elsevier |others=[[Krste Asanović]] |isbn=978-0-12-811905-1 |edition=6 |___location=Cambridge, Mass |pages=557}}</ref>

The TPU was designed to be a [[Coprocessor|co-processor]] communicating via a [[PCI Express|PCIe]] bus, to be easily incorporated in existing servers. It is primarily a [[Matrix multiplication|matrix-multiplication]] engine following a CISC (Complex Instruction Set Computer) [[Instruction set architecture|ISA]]. The multiplication engine uses [[Systolic array|systolic execution]] to save energy, reducing the number of writes to [[Volatile memory|SRAM]].<ref name=":2">{{Cite book |last1=Hennessy |first1=John L. |title=Computer architecture: a quantitative approach |last2=Patterson |first2=David A. |date=2019 |publisher=Morgan Kaufmann Publishers, an imprint of Elsevier |others=[[Krste Asanović]] |isbn=978-0-12-811905-1 |edition=6 |___location=Cambridge, Mass |pages=560}}</ref>