Successive-approximation ADC: Difference between revisions

Revision as of 19:19, 3 January 2025

Revision as of 20:12, 3 January 2025

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===Examples===

'''Example 1:''' The ten steps to converting an analog input to 10 9-bit digital, using successive-approximation, are shown here for all voltages from 5 V to 0 V in 0.1 V iterations. Since the reference voltage is 5 V, when the input voltage is also 5 V, all bits are set. As the voltage is decreased to 4.9 V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5 V.

The binary weights assigned to each bit, starting with the MSB, are 2.5, 1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125, 0.009765625, 0.0048828125. All of these add up to 4.9951171875, meaning binary 1111111111111111111, or one LSB less than 5.

When the analog input is being compared to the internal DAC output, it effectively is being compared to each of these binary weights, starting with the 2.5 V and either keeping it or clearing it as a result. Then by adding the next weight to the previous result, comparing again, and repeating until all the bits and their weights have been compared to the input, the result, a binary number representing the analog input, is found.

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# Initialize register with MSB set to 1 and all other values set to zero.

# In the n-{{Sup|th}} clock cycle, if voltage is higher than digital equivalent voltage of the number in register, the (n+1)-{{Sup|th}} digit from the left is set to 1. If the voltage were lower than digital equivalent voltage, then n-{{Sup|th}} digit from left is set to zero and the next digit is set to 1. To perform a conversion, an N-bit ADC requires N such clock cycles excluding the initial state.

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