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{{See also|#Operations to read a data bit from a DRAM storage cell}}
Dynamic memory, by definition, requires periodic refresh. Furthermore, reading 1T dynamic memory is a destructive operation, requiring a recharge of the storage cells in the row that has been read. If these processes are imperfect, a read operation can cause [[soft error]]s. In particular, there is a risk that some charge can leak between nearby cells, causing the refresh or read of one row to cause a ''disturbance error'' in an adjacent or even nearby row. The awareness of disturbance errors dates back to the first commercially available DRAM in the early 1970s (the [[Intel 1103]]). Despite the mitigation techniques employed by manufacturers, commercial researchers proved in a 2014 analysis that commercially available [[DDR3]] DRAM chips manufactured in 2012 and 2013 are susceptible to disturbance errors.<ref>{{cite web | url = http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_kim_talk_isca14.pdf | title = Flipping Bits in Memory Without Accessing Them: DRAM Disturbance Errors | date = June 24, 2014 | access-date = March 10, 2015 | author1 = Yoongu Kim | author2 = Ross Daly | author3 = Jeremie Kim | author4 = Chris Fallin | author5 = Ji Hye Lee | author6 = Donghyuk Lee | author7 = Chris Wilkerson | author8 = Konrad Lai | author9 = Onur Mutlu | website = ece.cmu.edu | url-status = live | archive-url = https://web.archive.org/web/20150326080426/http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_kim_talk_isca14.pdf | archive-date = 2015-03-26 }}</ref> The associated side effect that led to observed bit flips has been dubbed ''[[row hammer]]''.
==Packaging==
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