Memory hierarchy: Difference between revisions

Revision as of 01:01, 26 October 2024

Revision as of 19:17, 11 January 2025

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{{distinguish|Learning pyramid}}

In [[computer architecture]], the '''memory hierarchy''' separates [[computer storage]] into a hierarchy based on [[Response time (technology)|response time]]. Since response time, [[Computational complexity|complexity]], and [[Computer data storage|capacity]] are related, the levels may also be distinguished by their [[Computer performance|performance]] and controlling technologies.<ref name="toyzee" /> Memory hierarchy affects performance in computer architectural design, algorithm predictions, and lower level [[computer programming|programming]] constructs involving [[locality of reference]].

Designing for high performance requires considering the restrictions of the memory hierarchy, i.e. the size and capabilities of each component. Each of the various components can be viewed as part of a hierarchy of memories {{math|(''m''₁, ''m''₂, ..., ''m_n'')}} in which each member {{mvar|m_i}} is typically smaller and faster than the next highest member {{math|''m''_''i''+1}} of the hierarchy. To limit waiting by higher levels, a lower level will respond by filling a buffer and then signaling for activating the transfer.

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* ''Internal'' &ndash; [[Processor register]]sregisters and [[CPU cache|cache]].

* Main &ndash; the system [[Random-access memory|RAM]] and controller cards.

* On-line mass storage &ndash; Secondary storage.

* Off-line bulk storage &ndash; Tertiary and Off-line storage.

This is a general memory hierarchy structuring. Many other structures are useful. For example, a paging algorithm may be considered as a level for [[virtual memory]] when designing a [[computer architecture]], and one can include a level of [[nearline storage]] between online and offline storage.

==Properties of the technologies in the memory hierarchy==