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* '''System Reset''' sends a reset signal on every I/O channel and clears the processor state; all pending interruptions are cancelled. System Reset is not guaranteed to correct parity errors in general registers, floating point registers or storage. System Reset does not reset the state of shared I/O devices.
* '''{{anchor|Initial_Program_Load}}Initial Program Load''' (IPL)<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=123}} is a process for loading a program when there isn't a loader available in storage, usually because the machine was just powered on or to load an alternative operating system.<ref name=A22-6821-7/>{{rp|page=123}} This process is sometimes known as [[Booting]].
:: As part of the IPL facility the operator has a means of specifying a 12-bit<ref group=NB name=ChanNum/> device address, typically with three dials as shown in the operator controls drawing. When the operator<ref group=NB>Or an equivalent automated facility.</ref> selects the ''Load'' function, the system performs a ''System Reset'', sends a Read IPL<ref group=NB>Read with all modifier bits zero</ref> channel command to the selected device in order to read 24 bytes into locations 0-23 and causes the channel to begin fetching ''CCW''s at ___location 8; the effect is as if the channel had fetched a CCW with a length of 24, and address of 0 and the flags containing Command Chaining + Suppress Length Indication. At the completion of the operation, the system stores the I/O address in the halfword at ___location 2 and loads the PSW from ___location 0.
:: Initial program loading is typically done from a tape, a card reader, or a disk drive. Generally, the operating system was loaded from a disk drive; IPL from tape or cards was used only for diagnostics or for installing an operating system on a new computer.
* '''Emergency pull switch'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} (Emergency power off, EPO) sends an EPO signal to every I/O channel, then turns off power to the processor complex. Because EPO bypasses the normal sequencing of power down, damage can result, and the EPO control has a mechanical latch to ensure that a customer engineer inspects the equipment before attempting to power it back on.
* '''Power on'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} powers up all components of the processor complex and performs a system reset.
* '''Power off'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} initiates an orderly power-off sequence. Although the contents of storage are preserved, the associated storage keys may be lost.
* The '''Interrupt''' key<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} causes an [[#External interruption|external interruption]] with bit 25 set in the External Old PSW.
* The '''Wait light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} indicates that the [[#Program Status Word (PSW)|PSW]] has bit 14 (wait) set; the processor is temporarily halted but resumes operation when an interruption condition occurs.
* The '''Manual light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} indicates that the CPU is in a stopped state.
* The '''System light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} indicates that a meter is running, either due to CPU activity or due to I/O channel activity.
* The '''Test light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} indicates that certain operator controls are active, when certain facilities, e.g., INSTRUCTION STEP, have been used by a Diagnose instruction or when abnormal thermal conditions exist. The details are model dependent.
* The '''Load light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=124}} is turned on by IPL and external start. It is turned off by loading the PSW from ___location 0 at the completion of the load process.
* The '''Load unit'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagespp=124–125}} controls provide the rightmost 11<ref group=NB>There is an inconsistency, in that ''Interruptions from More than Seven Channels''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=121.4}} allows for more channels.</ref> bits of the device from which to perform an IPL.
* The '''Load Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} starts the [[#Initial Program Load|IPL]] sequence.
* The '''Prefix Select Key Switch'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} selects whether [[#Initial Program Load|IPL]] will use the primary prefix or the alternative prefix.
* The '''System-Reset Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} initiates a [[#System Reset|System Reset]].
* The '''Stop Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} puts the CPU in a stopped state; channel programs continue running and interruption conditions remain pending.
* The '''Rate Switch'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} determines the mode in which the processor fetches instructions. Two modes are defined by the architecture:
** PROCESS
** INSTRUCTION STEP
* The '''Start Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=125}} initiates instruction fetching in accordance with the setting of the [[#Rate Switch|Rate Switch]].
* The '''Storage-Select Switch'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} determines the type of resource accessed by the [[#Store Key|Store Key]] and [[#Display Key|Display Key]]. Three selections are defined by the architecture:
** Main storage
** General registers
** Floating-point registers
* The '''Address Switches'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} specify the address or register number for the [[#Store Key|Store Key]], [[#Display Key|Display Key]] and, on some models, the [[#Set IC Key|Set IC Key]]..
* The '''Data Switches'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} specify the data for the [[#Store Key|Store Key]] and, on some models, the [[#Set IC Key|Set IC Key]].
* The '''Store Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} stores the value in the [[#Data Switches|Data Switches]] as specified by the [[#|Storage-Select Switch]] and the [[#Address Switches|Address Switches]].
* The '''Display Key'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} displays the value specified by the [[#|Storage-Select Switch]] and the [[#Address Switches|Address Switches]].
* The '''Set IC='''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} sets the instruction address portion of the PSW from the [[#Data Switches|Data Switches]] or the [[#Address Switches|Address Switches]], depending on the model.
* The '''Address-Compare Switches'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} select the mode of comparison and what is compared. Stop on instruction address compare is present on all models, but stop on data address compare is only present on some models.
* The '''Alternate-Prefix Light'''<sup class=reference>[[#PoOps{{sfn|PoOps]]</sup>{{rp|pagep=126}} is on when the prefix trigger is in the alternate state.
==Optional features==
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