Capability Hardware Enhanced RISC Instructions: Difference between revisions

Revision as of 08:44, 27 January 2025

Revision as of 09:36, 27 January 2025

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* '''CHERIoT''':<ref name="cheriot" /> Introduced by Microsoft in 2023<ref>{{cite tech report |author1=Saar Amar |author2=Tony Chen |author3=David Chisnall |author4=Felix Domke |author5=Nathaniel Filardo |author6=Kunyan Liu |author7=Robert Norton-Wright |author8=Yucong Tao |author9=Robert N. M. Watson |author10=Hongyan Xia |title=CHERIoT: Rethinking security for low-cost embedded systems |id=MSR-TR-2023-6 |date=February 2023 |publisher=Microsoft |url=https://www.microsoft.com/en-us/research/publication/cheriot-rethinking-security-for-low-cost-embedded-systems/}}</ref> and now developed by multiple vendors,<ref>{{cite web |url=https://cheriot.org/govenance/organisation/2024/11/01/cheriot-administration.html |title=Who controls the CHERIoT project? |date=November 2024 |access-date=20 January 2025 }}</ref> CHERIoT is a RISC-V CHERI adaptation optimised for small embedded devices. CHERIoT is a hardware-software co-designed project and builds a custom RTOS and compartment model along with specialised hardware to provide string security guarantees. It incorporates advanced memory safety features inspired by the CHERI temporal safety projects performed on Morello.

* '''Sonata''':<ref>{{cite web |url=https://www.sunburst-project.org |title=Welcome to the Sunburst Project |publisher=lowRISC |access-date=20 January 2025}}</ref> Developed by [[lowRISC]] and manufactured by NewAE as part of the UKRI-funded Sunburst project, the Sonata platform is an FPGA-based system designed to run RISC-V architectures. The board has an open-source design, allowing researchers and developers to modify and adapt its hardware and software. Sonata is primarily designed as a prototyping system for CHERIoT.

* '''X730''':<ref>{{Cite web |title=Codasip Protects Memory With Cheri {{!}} TechInsights |url=https://www.techinsights.com/blog/codasip-protects-memory-cheri |access-date=2025-01-27 |website=www.techinsights.com}}</ref> Released by [[Codasip]] in 2024, this processor IP is an implementation of the draft RISC-V CHERI standard for an application-class processor.

* '''ICENI''': Announced by SCI SemiconductorsSemiconductor in 2024,<ref name="iceni" /> ICENI is a CHERIoT-compatible microcontroller designed for secure embedded systems.

CHERI implementations that target mainstream operating systems, are designed to accommodate both legacy and pure capability software, to allowallowing for gradual adaptation for existing applications. CHERI has also been implemented across various hardware architectures in a research setting, including MIPS,<ref name=isca /> AArch64 (via the Morello platform), and RISC-V.<ref>{{cite web |url=https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-risc-v.html#cores |title=CHERI-Piccolo, CHERI-Flute, and CHERI-Toooba CPU cores on FPGA |access-date=24 January 2025}}</ref>

== History ==