Comparison of instruction set architectures: Difference between revisions

Revision as of 13:02, 4 February 2025

Revision as of 14:53, 4 February 2025

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| Register–Memory<br />Memory–Memory<br /> Register–Register

| CISC

| 16 general<br />16 control (S/370 and later)<br />16 access (ESA/370 and later)<br>32 vector registers (z13 and later)<!-- 16× 64/32-bit general purpose registers, 16× 64-bit floating point registers, 16× 32-bit access registers, 16× 64/32-bit control registers, 16× 512-bit vector registers (3090 and ES/9000 only) , 32/128-bit vector registers (z13 and later) -->

| Variable <small>(16-, 32-, or 48-bit)</small>

| Condition code, compare and branch {{bracket|auto increment}}, Branch-Counter auto-decrement

| Big

|