Revision as of 14:53, 4 February 2025 edit Chatul (talk \| contribs) Extended confirmed users 8,441 edits →Instruction sets: z/Architecture vector registers ← Previous edit		Revision as of 19:16, 4 February 2025 edit undo RastaKins (talk \| contribs) Extended confirmed users 2,113 edits →Instruction sets: Added Data General Nova Next edit →
Line 613: \| {{No}} \| {{partial\|On Altera/Intel FPGA only}} \|- \| [[Data General Nova\|Nova]] \| 16 \| \| 1969 \| 2 \| Register–Register \| CISC \| 4 \| Fixed <small>(16-bit)</small> \| Skip \| None \| \| \| \|- \| [[NS320xx]]

Comparison of instruction set architectures: Difference between revisions