AVR microcontrollers: Difference between revisions

Revision as of 23:22, 13 February 2025

Revision as of 22:52, 14 February 2025

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* 12-bit ADC

* 10-bit DAC

* '''AVR DA-series''' (early 2020) – The high memory density makes these MCUs well suited for both wired and wireless communication-stack-intensive functions.

** integrated sensors for capacitative touch measurement ([[Human–computer interaction|HCI]])

** updated core independent peripherals ([[Autonomous peripheral operation|CIPs]]) and a analog perihperals

** no external high frequency crystal

* '''AVR DB-series''' (mid-late 2020) – inherits many features from the DA-family, while adding its own:

** 2 or 3 on-chip opamps

** MultiVoltage IO (MVIO) on PORTC

** Supports external HF crystal

* '''AVR DD-series'''

** 16–64 KiB Flash

** 2–8 KiB SRAM

** 14–32-pin package

** internal 24  MHz oscillator

** 7–23-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC)

** no amplifiers

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** Multi-Voltage Input/Output (MVIO) support on 3 or 4 pins on Port C

** 4 Configurable Custom Logic (CCL) cells, 6 Event System channels

* '''AVR EA-series'''

** 8–64 KiB Flash

** 28–48-pin package

** internal 20  MHz oscillator

** 24–32-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC)

** Programmable Gain Amplifier (PGA) with up to 16x gain

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* avr_core,<ref>{{cite web|url=http://opencores.org/project,avr_core|title=AVR Core :: Overview|publisher=OpenCores|access-date=2012-09-19}}</ref> written in [[VHDL]], is a clone aimed at being as close as possible to the ATmega103.

* Navré,<ref>{{cite web|url=http://opencores.org/project,navre|title=Navré AVR clone (8-bit RISC) Overview|publisher=OpenCores|access-date=2012-09-19}}</ref> written in [[Verilog]], implements all [[Atmel AVR instruction set|Classic Core]] instructions and is aimed at high performance and low resource usage. It does not support [[interrupt]]s.

* softavrcore,<ref>{{cite web|url=https://opencores.org/projects/softavrcore|title=Soft AVR Core + Interfaces Overview|publisher=OpenCores|access-date=2020-06-16}}</ref> written in [[Verilog]], implements the [[AVR instruction set]] up to AVR5, supports interrupts along with optional automatic interrupt acknowledgement, power saving via [[Idle (CPU)|sleep mode]] plus some peripheral interfaces and [[Hardware_accelerationHardware acceleration|hardware accelerators]] (such as [[UART]], [[Serial_Peripheral_InterfaceSerial Peripheral Interface|SPI]], [[cyclic redundancy check]] calculation unit and [[Programmable_interval_timerProgrammable interval timer|system timers]]). These peripherals demonstrate how could these be attached to and configured for this core. Within the package, a full-featured [[FreeRTOS]] port is also available as an example for the core + peripheral utilization.

* The opencores project CPU lecture<ref>{{cite web|url=http://opencores.org/project,cpu_lecture|title=CPU lecture|publisher=OpenCores|access-date=2015-02-16}}</ref> written in [[VHDL]] by Dr. Jürgen Sauermann explains in detail how to design a complete AVR-based [[system on a chip]] (SoC).

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== External links ==

{{Commons category|Atmel AVR}}

{{Wikibooks|Embedded Systems|Atmel AVR}}

{{Portal|Electronics}}