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|<ref name="Intel-Product-Timeline"/><ref name="shmj-1970s-sram">{{cite web |title=1970s: SRAM evolution |url=http://www.shmj.or.jp/english/pdf/ic/exhibi724E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019}}</ref><ref name="Pimbley">{{cite book |last1=Pimbley |first1=J. |title=Advanced CMOS Process Technology |date=2012 |publisher=[[Elsevier]] |isbn=9780323156806 |page=7 |url=https://books.google.com/books?id=8EUWHSqevQoC&pg=PA7}}</ref><ref>{{Cite web|url=https://www.intel-vintage.info/intelmemory.htm|title=Intel Memory|website=Intel Vintage|access-date=2019-07-06|ref=intel-memory|archive-date=2022-03-19|archive-url=https://web.archive.org/web/20220319073833/https://www.intel-vintage.info/intelmemory.htm|url-status=
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|rowspan="2" |<ref name="HB19950109">{{usurped|1=[https://web.archive.org/web/20140827092848/http://business.highbeam.com/3591/article-1G1-16482653/breaking-gigabit-barrier-drams-isscc-portend-major ''Breaking the gigabit barrier, DRAMs at ISSCC portend major system-design impact. (dynamic random access memory; International Solid-State Circuits Conference; Hitachi Ltd. and NEC Corp. research and development)'']}}, January 9, 1995</ref><ref name="smithsonian-japan"/>
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|Hitachi
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