Serial Peripheral Interface: Difference between revisions

Revision as of 03:00, 27 February 2025

Revision as of 04:32, 27 February 2025

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'''Serial Peripheral Interface''' ('''SPI''') is a <!--DO NOT ITALICIZE; CONSIDERED ANGLICIZED-->[[de facto standard]] (with many [[#Variations|variants]]) for [[Comparison of synchronous and asynchronous signalling|synchronous]] [[serial communication]], used primarily in [[embedded systems]] for short-distance [[wired communication]] between [[integrated circuits]].

SPI follows a [[master–slave (technology)|master–slave architecture]],<ref name=":0">{{Cite web |last=DhakerStoicescu |first=PiyuAlin |date=2018 |title=IntroductionGetting toStarted with SPI Interface |url=https://wwwww1.analogmicrochip.com/downloads/en/analog-dialogueAppnotes/articles/introductionTB3215-toGetting-spiStarted-with-SPI-interface90003215A.htmlpdf |url-status=live |archive-url=https://web.archive.org/web/20230525152752/https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html |archive-date=2023-05-25 |access-date=2023-07-21 |website=[[Analog DialogueMicrochip]]}}</ref> where a master device [[Signaling (telecommunications)|orchestrates communication]] with one or more slave devices by driving the [[clock signal|clock]] and [[chip select]] signals. Some devices support changing master and slave roles on the fly.

[[Motorola]]'s original specification (from the early 1980s) uses four [[logic signal]]s, aka lines or wires, to support [[full duplex]] communication. It is sometimes called a ''four-wire'' [[serial bus]] to contrast with [[Serial Peripheral Interface#Three-wire|three-wire]] variants which are [[half duplex]], and with the ''two-wire'' [[I²C]] and [[1-Wire]] serial buses.

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During each SPI clock cycle, full-duplex transmission of a single bit occurs. The master sends a bit on the MOSI line while the slave sends a bit on the MISO line, and then each reads their corresponding incoming bit. This sequence is maintained even when only one-directional data transfer is intended.

Transmission using a single slave (Figure 1) involves one shift register in the master and one shift register in the slave, both of some given word size (e.g. 8 bits),{{NoteTag|Transmissions. The transmissions often consist of eight-bit words. However, but other word-sizes are also common, for example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC2101 by Texas Instruments, or twelve-bit words for many digital-to-analog or analog-to-digital converters.}} connected in a virtual [[ring topology]].

Data is usually shifted out with the [[most-significant bit]] (MSB) first.{{NoteTag|The but the original specification has a LSBFE ("LSB-First Enable") to control whether data is transferred least (LSB) or most significant bit (MSB) first.}} On the clock edge, both master and slave shift out a bit to its counterpart. On the next clock edge, each receiver samples the transmitted bit and stores it in the shift register as the new least-significant bit. After all bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave.

If a single slave device is used, its {{Overline|SS}} pin ''may'' be fixed to [[logic level|logic low]] if the slave permits it. With multiple slave devices, a [[#Multidrop configuration|multidrop configuration]] requires an independent {{Overline|SS}} signal from the master for each slave device, while a [[#Daisy chain configuration|daisy-chain configuration]] only requires one {{Overline|SS}} signal.