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PaulBoddie (talk | contribs) m →Code density: Reworded the start of the paragraph after the newly introduced material to reference the topic under discussion. Perhaps "complaint" should be moderated to "concern", however. |
→Concept: 8086 instructions can be up to six bytes, not including segment override. |
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[[Microprocessor]]s encode their instructions as a series of [[bit]]s, normally divided into a number of 8-bit [[byte]]s. For instance, in the [[MOS 6502]], the {{code|ADC}} instruction performs binary addition between an operand value and the value already stored in the [[Accumulator (computing)|accumulator]]. There are a variety of places the processor might find the operand; it might be located in [[main memory]], or in the special [[zero page]], or be an explicit constant like "10". Each of these variations used a different 8-bit instruction, or [[opcode]]; if one wanted to add the constant 10 to the accumulator the instruction would be encoded in memory as {{code|$69 $0A}}, with $0A being [[hexadecimal]] for the decimal value 10. If it was instead adding the value stored in main memory at ___location $4400, it would be {{code|$6D $00 $44}}, with a [[Endianness|little-endian]] address.{{sfn|Verts|2004}}
Note that the second instruction requires three bytes because the memory address is 16 bits long. Depending on the instruction, it might use one, two, or three bytes.{{sfn|Verts|2004}} This is now known as a [[variable length instruction set]], although that term was not common at the time as most processors, including [[mainframe]]s and [[minicomputer]]s, normally used some variation of this concept. Even in the late 1970s, as microprocessors began to move from 8-bit formats to 16, this concept remained common; the [[Intel
It was during the move to 32-bit systems, and especially as the [[RISC]] concept began to take over processor design, that variable length instructions began to go away. In the [[MIPS architecture]], for instance, all instructions are a single 32-bit value, with a 6-bit opcode in the [[most significant bit]]s and the remaining 26 bits used in various ways representing its limited set of addressing modes. Most RISC designs are similar. Moving to a fixed-length instruction format was one of the key design concepts behind the performance of early RISC designs; in earlier systems the instruction might take one to six memory cycles to read, requiring wiring between various parts of the logic to ensure the processor didn't attempt to perform the instruction before the data was ready. In RISC designs, operations normally take one cycle, greatly simplifying the decoding. The savings in these interlocking circuits is instead applied to additional logic or adding [[processor register]]s, which have a direct impact on performance.<ref>{{cite web |url=http://www.cs.uwm.edu/classes/cs315/Bacon/Lecture/HTML/ch05s07.html |title=MIPS Instruction Code Formats |website=Computer Science 315 Lecture Notes |first=Jason |last=Bacon |access-date=2021-04-09 |archive-date=2019-07-17 |archive-url=https://web.archive.org/web/20190717133605/http://www.cs.uwm.edu/classes/cs315/Bacon/Lecture/HTML/ch05s07.html |url-status=dead }}</ref>
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