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m →Instruction sets: sort-under, {{verth}} |
m →Instruction sets: {{verth}} |
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Line 150:
| [[Complex instruction set computer|CISC]]
| 3
| Variable <br/><small>(8- to 24-bit)</small>
| Condition register
| Little
Line 165:
| CISC
| 3
| Variable <br/><small>(8- to 24-bit)</small>
| Condition register
| Big
Line 180:
| CISC
| 5
| Variable <br/><small>(8- to 32-bit)</small>
| Condition register
| Big
Line 210:
| CISC
| 7
| Variable <br/><small>(8 to 24 bits)</small>
| Condition register
| Little
Line 218:
|-
| [[8051]]
| 32 <br/><small>(8→32)</small>
|
| 1977?
Line 225:
| CISC
| {{ubl|32 in 4-bit|16 in 8-bit|8 in 16-bit|4 in 32-bit}}
| Variable <br/><small>(8 to 24 bits)</small>
| Compare and branch
| Little
Line 236:
| v4 (x86-64)
| 1978
| 2 (integer)<br />3 ([[Advanced Vector Extensions|AVX]]){{efn|The LEA (all processors) and IMUL-immediate (80186 & later) instructions accept three operands; most other instructions of the base integer ISA accept no more than two operands.}}<br />4 ([[FMA instruction set|FMA4]] and <code>VPBLENDVPx</code>)<br/><ref>{{cite web|url=https://www.amd.com/system/files/TechDocs/43479.pdf|title=AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions|date=November 2009|publisher=[[AMD]]}}</ref><br />
| Register–Memory
| CISC
| {{ubl|8 (+ 4 or 6 segment reg.) <br/><small>(16/32-bit)</small>| 16 (+ 2 segment reg. gs/cs) <br/><small>(64-bit)</small>| 32 with AVX-512 and Advance Performance eXtension (apx)}}<!-- general-purpose registers; floating-point stack and SSE registers not counted -->
| Variable<!-- 1 to 5 bytes --> <br/><small>(8086 ~ 80386: variable between 1 and 6 bytes /w MMU + intel SDK, 80486: 2 to 5 bytes with prefix, pentium and onward: 2 to 4 bytes with prefix, x64: 4 bytes prefix, third party x86 emulation: 1 to 15 bytes w/o prefix & MMU . SSE/MMX: 4 bytes /w prefix AVX: 8 Bytes /w prefix)</small>
| Condition code
| Little
Line 255:
| [[Reduced instruction set computer|RISC]]
| 32 (including "zero")<!-- 31 64-bit GPRs, 31 64-bit FPRs, one of both is hardwired zero -->
| Fixed <br/><small>(32-bit)</small>
| Condition register
| Bi
Line 264:
| [[ARC (processor)|ARC]]
| 16/32/64 (32→64)
| ARCv3<br/><ref>{{Cite web|url=https://news.synopsys.com/2020-04-07-Synopsys-Introduces-New-64-bit-ARC-Processor-IP-Delivering-Up-to-3x-Performance-Increase-for-High-End-Embedded-Applications|title = Synopsys Introduces New 64-bit ARC Processor IP Delivering up to 3x Performance Increase for High-End Embedded Applications}}</ref>
| 1996
| 3
Line 270:
| RISC
| 16 or 32 including SP <br /> user can increase to 60
| Variable <br/><small>(16- or 32-bit)</small>
| Compare and branch
| Bi
Line 285:
| RISC
| {{ubl|15}}
| Fixed <br/><small>(32-bit)</small>
| Condition code
| Bi
Line 300:
| RISC
| {{ubl|7 with 16-bit Thumb instructions|15 with 32-bit Thumb-2 instructions}}
| Thumb: Fixed <br/><small>(16-bit)</small>, Thumb-2:<br />Variable <br/><small>(16- or 32-bit)</small>
| Condition code
| Bi
Line 309:
| [[ARM architecture#64/32-bit architecture|Arm64/A64]]
| 64
| v8.9-A/v9.4-A,<br/><ref>{{Cite web |title=Arm A-Profile Architecture Developments 2022 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022 |access-date=2022-12-09 |website=community.arm.com |date=29 September 2022 |language=en}}</ref> Armv8-R<br/><ref>{{cite news |last=Frumusanu |first=Andrei |date=September 3, 2020 |url=https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor |title=ARM Announced Cortex-R82: First 64-bit Real Time Processor |website=[[AnandTech]]}}</ref>
| 2011<br/><ref>{{cite web |url= https://www.computerworld.com/article/1536136/arm-goes-64-bit-with-new-armv8-chip-architecture.html |title= ARM goes 64-bit with new ARMv8 chip architecture |website=[[Computerworld]] |date= 27 October 2011 |access-date= 8 May 2024}}</ref>
| 3
| Register–Register
| RISC
| 32 (including the stack pointer/"zero" register)
| Fixed <br/><small>(32-bit)</small>, Variable <br/><small>(32-bit or 64-bit for [[Fujitsu A64FX#Design|FMA4]] with 32-bit prefix<ref name="FujitsuHotChips">{{cite web |title=Hot Chips 30 conference; Fujitsu briefing |url=http://www.hotchips.org/hc30/2conf/2.13_Fujitsu_HC30.Fujitsu.Yoshida.rev1.2.pdf |archive-url=https://web.archive.org/web/20201205202434/https://hotchips.org/hc30/2conf/2.13_Fujitsu_HC30.Fujitsu.Yoshida.rev1.2.pdf |archive-date=2020-12-05 |url-status=dead |author=Toshio Yoshida |publisher=Fujitsu}}</ref><!-- See slide 9 and 10: "For SVE, four-operand “FMA4” requires a prefix instruction (MOVPRFX) followed by destructive 3-operand FMA3" -->)</small>
| Condition code
| Bi
Line 345:
| RISC
| 15 <!-- Up to 15× general-purpose 32-bit registers -->
| Variable<br/><ref>{{cite web | url= https://ww1.microchip.com/downloads/en/devicedoc/doc32000.pdf | title= AVR32 Architecture Document | publisher= [[Atmel]] | access-date= 2024-05-08}}</ref>
|
| Big <!-- have special endian-translating load and store instructions -->
Line 356:
|
| 2000
|3<br/><ref>{{Cite web|url=https://www.analog.com/media/en/dsp-documentation/processor-manuals/blackfin_pgr_rev2.2.pdf|title=Blackfin manual|website=analog.com}}</ref>
| Register–Register
| RISC<br/><ref>{{cite web | url= https://www.analog.com/en/lp/001/blackfin-architecture.html | title= Blackfin Processor Architecture Overview | publisher= [[Analog Devices]] | access-date= 2024-05-08}}</ref>
| 2 accumulators
8 data registers
Line 369:
| Variable (<small>16- or 32-bit</small>)
| Condition code
| Little<br/><ref>{{cite web | url= http://www.analog.com/FAQs/FAQDisplay.html?DSPKBContentID=752A11D1-9E11-4A7F-91AC-CA3C264C5667 | title= Blackfin memory architecture | publisher= [[Analog Devices]] | access-date= 2009-12-18 | archive-url= https://web.archive.org/web/20110616182409/http://www.analog.com/FAQs/FAQDisplay.html?DSPKBContentID=752A11D1-9E11-4A7F-91AC-CA3C264C5667 | archive-date= 2011-06-16 | url-status= dead }}</ref>
|
|
Line 382:
| CISC
| 48-bit A reg., 48-bit Q reg., 6 15-bit B registers, miscellaneous
| Variable <br/><small>(24- or 48-bit)</small>
| Multiple types of jump and skip
| Big
Line 397:
| n/a{{efn|partly RISC: load/store architecture and simple addressing modes, partly CISC: three instruction lengths and no single instruction timing}}
| 24 (8 18-bit address reg.,<br />8 18-bit index reg.,<br />8 60-bit operand reg.)
| Variable <br/><small>(15-, 30-, or 60-bit)</small>
| Compare and branch
| n/a{{efn|Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big-endian semantics.}}
Line 412:
| CISC
| 1 18-bit A register, locations 1–63 serve as index registers for some instructions
| Variable <br/><small>(12- or 24-bit)</small>
| Test A register, test channel
| n/a{{efn|Since memory is an array of 12-bit words with no means to access sub-units, big endian vs. little endian makes no sense.}}
Line 427:
| [[Very long instruction word|VLIW]]<ref name="crusoe-arch" /><ref name="technology-behind-crusoe">{{cite web |url=http://www.cs.ucf.edu/~lboloni/Teaching/EEL5708_2004/slides/paper_aklaiber_19jan00.pdf |title=The Technology Behind Crusoe Processors |author=Alexander Klaiber |publisher=Transmeta Corporation |date=January 2000 |access-date=December 6, 2013}}</ref>
| {{ubl|1 in native push stack mode|6 in x86 emulation +<br />8 in x87/MMX mode +<br />50 in rename status|12 integer + 48 shadow +<br />4 debug in native VLIW|mode<ref name="crusoe-arch" /><ref name="technology-behind-crusoe" />}}
| Variable <br/><small>(64- or 128-bit in native mode, 15 bytes in x86 emulation)</small><ref name="technology-behind-crusoe" />
| Condition code<ref name="crusoe-arch" />
| Little
Line 457:
| RISC
| 32
| Fixed <br/><small>(32-bit)</small>
| Condition register
| Big
Line 502:
| [[Explicitly parallel instruction computing|EPIC]]
| 128 <!-- 128× 64-bit general purpose registers, 128× 80-bit floating-point registers, 64× 1-bit predicate registers -->
| Fixed <br/><small>(128-bit bundles with 5-bit template tag and 3 instructions, each 41-bit long)</small>
| Condition register
| Bi<br /><small>(selectable)</small>
Line 532:
| RISC
| 16 <!-- 16× 32-bit registers -->
| Variable <br/><small>(16- or 32-bit)</small>
|Condition register
| Bi
Line 547:
| RISC
| 32
| Fixed <br/><small>(32-bit)</small>
| Compare and branch
| Big
Line 561:
| Register–Register
| RISC
| 32<br/><ref>{{cite web | url= http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32architecture.cfm | title= LatticeMico32 Architecture | publisher= [[Lattice Semiconductor]] |url-status =dead|archive-url = https://web.archive.org/web/20100623021729/http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32architecture.cfm |archive-date = 23 June 2010}}</ref>
| Fixed <br/><small>(32-bit)</small>
| Compare and branch
| Big
| User-defined instructions
| {{Yes}}<br/><ref>{{cite web | url= http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32opensourcelicensing.cfm | title= LatticeMico32 Open Source Licensing | publisher= [[Lattice Semiconductor]] |url-status = dead|archive-url = https://web.archive.org/web/20100620185845/http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32opensourcelicensing.cfm|archive-date = 20 June 2010}}</ref>
| {{Yes}}
|-
| [[MIPS architecture|MIPS]]
| 64 <br/><small>(32→64)</small>
| 6<br/><ref>[https://www.mips.com/products/architectures/mips64/ MIPS64 Architecture for Programmers: Release 6]</ref><br/><ref>[https://www.mips.com/products/architectures/mips32-2/ MIPS32 Architecture for Programmers: Release 6]</ref>
| 1981
| 1–3
Line 577:
| RISC
| 4–32 (including "zero")<!-- 15× 32-bit GPRs (R0=0), 16× 32-bit FP regs (paired DP). MIPS64 has 31× 64-bit GPRs. R0=0 sometimes counted as 32nd GPR, but isn't. Some customized chip may have much fewer register in order to fixed the custom instruction set for specific use, ex: Emotion engine -->
| Fixed <br/><small>(32-bit)</small>
| Condition register
| Bi
| [[MDMX]], [[MIPS-3D]]
| {{No}}
| {{No}}<br/><ref>[https://www.mipsopen.com/ MIPS Open]</ref><br/><ref>{{Cite web|url=https://www.hackster.io/news/wave-computing-closes-its-mips-open-initiative-with-immediate-effect-zero-warning-e88b0df9acd0|title = Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning}}</ref>
|-
| [[MMIX]]
Line 592:
| RISC
| 256 <!-- 256× 64-bit general-purpose registers and 32× 64-bit special-purpose registers -->
| Fixed <br/><small>(32-bit)</small>
| Condition register
| Big
Line 622:
| CISC
| 4
| Fixed <br/><small>(16-bit)</small>
| Skip
| None
Line 646:
| [[OpenRISC]]
| 32, 64
| 1.4<br/><ref>[https://openrisc.io/architecture OpenRISC Architecture Revisions]</ref> <!-- 2022-02-20 -->
| 2000
| 3
Line 660:
|-
| [[PA-RISC]]<br />(HP/PA)
| 64 <br/><small>(32→64)</small>
| 2.0 <!-- 1996 -->
| 1986
Line 667:
| RISC
| 32
| Fixed <br/><small>(32-bit)</small>
| Compare and branch
| Big → Bi <!-- 1.0 is big-endian, 1.1 and 2.0 are bi-endian -->
Line 674:
|
|-
|[[PDP-5]]<br/><ref>{{Cite book|url=http://www.bitsavers.org/pdf/dec/pdp5/F-55_PDP5Handbook_Feb64.pdf|title=PDP-5 Handbook|date=February 1964|publisher=[[Digital Equipment Corporation]]}}</ref><br> [[PDP-8]]<br/><ref>{{Cite book|url=http://www.bitsavers.org/pdf/dec/pdp8/pdp8/F-85_PDP-8_Users_Handbook_May66.pdf|title=PDP-8 Users Handbook|date=May 1966|publisher=[[Digital Equipment Corporation]]}}</ref>
| 12
|
Line 683:
| 1 accumulator
1 multiplier quotient register
| Fixed <br/><small>(12-bit)</small>
| Condition register
Test and branch
Line 699:
| CISC
| 8 (includes program counter and stack pointer, though any register can act as stack pointer)
| Variable <br/><small>(16-, 32-, or 48-bit)</small>
| Condition code
| Little
Line 707:
|-
| [[IBM POWER instruction set architecture|POWER]], [[PowerPC]], [[Power ISA]]
| 32/64 <br/><small>(32→64)</small>
| 3.1<ref name="POWER">{{cite web |title=Power ISA Version 3.1 |publisher=openpowerfoundation.org |date=2020-05-01 |url=https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0 |access-date=2021-10-20}}</ref>
| 1990
Line 714:
| RISC
| 32 GPR, 8 4-bit Condition Fields, Link Register, Counter Register
| Fixed <br/><small>(32-bit)</small>, Variable <br/><small>(32- or 64-bit with the 32-bit prefix<ref name="POWER" />)</small>
| Condition code, Branch-Counter auto-decrement
| Bi
Line 723:
| [[RISC-V]]
| 32, 64, 128
| 20191213<br/><ref>{{cite web |title=RISC-V ISA Specifications |url=https://riscv.org/specifications/ |access-date=17 June 2019}}</ref> <!-- Published: June 8, 2019 -->
| 2010
| 3
Line 767:
|-
| [[SPARC]]
| 64 <br/><small>(32→64)</small>
| OSA2017<br/><ref>[http://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-processor-2516655.html Oracle SPARC Processor Documentation]</ref>
| 1985
| 3
Line 774:
| RISC
| 32 (including "zero")<!-- 8 globals but %g0 always zero; at least 3 register windows of 16, not counting overlap -->
| Fixed <br/><small>(32-bit)</small>
| Condition code
| Big → Bi <!-- Historically big-endian, V9 is bi-endian -->
| [[Visual Instruction Set|VIS]]
| {{Yes}}
| {{Yes}}<br/><ref>[http://sparc.org/technical-documents/#ArchLic SPARC Architecture License]</ref>
|-
| [[SuperH]] (SH)
Line 789:
| RISC
| 16
| Fixed <br/><small>(16- or 32-bit)</small>, Variable
| Condition code<br />(single bit)
| Bi
Line 797:
|-
| [[IBM System/360 architecture|System/360]]<br />[[System/370]]<br />[[System/390]]<br />[[z/Architecture]]
| 64 <br/><small>(32→64)</small>
|
| 1964
Line 804:
| CISC
| 16 general<br />16 control (S/370 and later)<br />16 access (ESA/370 and later)<br>32 vector registers (z13 and later)<!-- 16× 64/32-bit general purpose registers, 16× 64-bit floating point registers, 16× 32-bit access registers, 16× 64/32-bit control registers, 16× 512-bit vector registers (3090 and ES/9000 only) , 32/128-bit vector registers (z13 and later) -->
| Variable <br/><small>(16-, 32-, or 48-bit)</small>
| Condition code, compare and branch {{bracket|auto increment}}, Branch-Counter auto-decrement
| Big
Line 819:
| VLIW
| 32 on C67x <br/> 64 on C67x+
| Fixed <br/><small>(256-bit bundles with 8 instructions, each 32-bit long)</small>
| Condition register
| Bi
Line 827:
|-
| [[Transputer]]
| 32 <br/><small>(4→64)</small>
|
| 1987
Line 834:
| [[Minimal instruction set computer|MISC]]
| 3 (as stack)
| Fixed <br/><small>(8-bit)</small>
| Compare and branch
| Little
Line 864:
| CISC
| 17
| Variable <br/><small>(8 to 32 bits)</small>
| Condition register
| Little
Line 871:
|
|-
! {{verth|Architecture}}
! Bits
! Version
! {{verth|Introduced}}
! Max #<br />[[operand]]s
! Type
Line 881:
! Instruction encoding
! [[Branch (computer science)|Branch]] evaluation
! {{verth|[[Endianness
! Extensions
! Open
| |||