Content deleted Content added
m →Instruction sets: {{verth}} |
m →Instruction sets: <br/>, {{n/a}} |
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Line 395:
| 3
| Register–Register
| {{n/a|N/A}}{{efn|partly RISC: load/store architecture and simple addressing modes, partly CISC: three instruction lengths and no single instruction timing}}
| 24 (8 18-bit address reg.,<br />8 18-bit index reg.,<br />8 60-bit operand reg.)
| Variable <br/><small>(15-, 30-, or 60-bit)</small>
| Compare and branch
| {{n/a|N/A}}{{efn|Since memory is an array of 60-bit words with no means to access sub-units, big endian vs. little endian makes no sense. The optional CMU unit uses big-endian semantics.}}
| Compare/Move Unit
| {{No}}
Line 414:
| Variable <br/><small>(12- or 24-bit)</small>
| Test A register, test channel
| {{n/a|N/A}}{{efn|Since memory is an array of 12-bit words with no means to access sub-units, big endian vs. little endian makes no sense.}}
| additional Peripheral Processing Units
| {{No}}
Line 425:
| 1
| Register–Register
| [[Very long instruction word|VLIW]]<br/><ref name="crusoe-arch" /><ref name="technology-behind-crusoe">{{cite web |url=http://www.cs.ucf.edu/~lboloni/Teaching/EEL5708_2004/slides/paper_aklaiber_19jan00.pdf |title=The Technology Behind Crusoe Processors |author=Alexander Klaiber |publisher=Transmeta Corporation |date=January 2000 |access-date=December 6, 2013}}</ref>
| {{ubl|1 in native push stack mode|6 in x86 emulation +<br />8 in x87/MMX mode +<br />50 in rename status|12 integer + 48 shadow +<br />4 debug in native VLIW|mode<ref name="crusoe-arch" /><ref name="technology-behind-crusoe" />}}
| Variable <br/><small>(64- or 128-bit in native mode, 15 bytes in x86 emulation)</small><ref name="technology-behind-crusoe" />
Line 881:
! Instruction encoding
! [[Branch (computer science)|Branch]] evaluation
! {{verth|[[Endianness
! Extensions
! Open
| |||