Comparison of instruction set architectures: Difference between revisions

Revision as of 12:08, 18 March 2025

Revision as of 18:32, 18 March 2025

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* In the "Type" column, "Register–Register" is a synonym for a common type of architecture, "[[load–store architecture|load–store]]", meaning that no instruction can directly access memory except some special ones, i.e. load to or store from register(s), with the possible exceptions of memory locking instructions for atomic operations.

* In the "Endianness" column, "Bi" means that the endianness is configurable.

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{| class="wikitable sticky-header sortable sort-under mw-datatable" border="1" style="font-size:85%;"

! {{verth|Architecture}}

! Bits

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|

|-

! {{verth|Architecture}}

! Bits

! Version

! {{verth|Introduced}}

! Max #<br />[[operand]]s

! Type

! Design <!-- Design Strategy/Philosophy -->

! [[Processor register|Registers]]<br />(excluding FP/vector)

! Instruction encoding

! [[Branch (computer science)|Branch]] evaluation

! {{verth|[[Endianness]]}}

! Extensions

! Open

! Royalty<br />free

|}