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→Real mode: Cleaned up math example with non-breaking spaces so that the binary numbers will not break and wrap. (This probably really ought to be formatted as a table or something like that.) |
→End-of-address space quirkiness: copy edit/language correction: this not referring to a space that is about the "end of address", it is quirkiness about the "end of address space". |
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{{anchor|Paragraph}}{{resize|105%|{{sidebox|above='''Example calculation:'''|text=A segment value of 0Ch (12) would give a linear address at C0h (192) in the linear address space. The address offset can then be added to this number. 0Ch:0Fh (12:15) would be C0h+0Fh=CFh (192+15=207), CFh (207) being the linear address.}}}}Each segment begins at a multiple of 16 bytes, called a ''paragraph'', from the beginning of the linear (flat) address space. That is, at 16 byte intervals. Since all segments are technically 64 KB long, this explains how overlap can occur between segments and why any ___location in the linear memory address space can be accessed with many segment:offset pairs. The actual ___location of the beginning of a segment in the linear address space can be calculated with ''segment'' × 16. Such address translations are carried out by the segmentation unit of the CPU.
=== End-of-address
{{main article|A20 line}}
The last segment, FFFFh (65535), begins at linear address FFFF0h (1048560), 16 bytes before the end of the 20-bit address space, and thus can access, with an offset of up to 65,536 bytes, up to 65,520 (65536−16) bytes past the end of the 20-bit 8088 CPU's address space. A further 4,094 next-highest 64K-segments also still cross that 1MB-threshold, but by less and less. On the 8088 CPU, these address accesses were wrapped around to the beginning of the address space such that 65535:16 would access address 0, and e.g. 65533:1000 would access address 952 of the linear address space. The fact that some programs written for the 8088 relied on this quirky wrap-around as a feature led to the [[Gate A20]] compatibility issues in later CPU generations, with the [[Intel 286]] and above, where the linear address space was expanded past 20 bits.
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