AVR microcontrollers: Difference between revisions

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In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (0000<sub>16</sub>–0FFF<sub>16</sub>). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space, which can be used optionally for mapping the internal EEPROM to the data address space (1000<sub>16</sub>–1FFF<sub>16</sub>). The actual SRAM is located after these ranges, starting at 2000<sub>16</sub>.
 
==== General-purpose input/output (GPIO) ports ====
Each [[GPIO]] port on a tiny or mega AVR drives up to eight pins and is controlled by three 8-bit registers: DDR''x'', PORT''x'' and PIN''x'', where ''x'' is the port identifier.