Dynamic random-access memory: Difference between revisions

Revision as of 15:40, 10 May 2025

Revision as of 20:56, 1 June 2025

Line 167:

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|+ Synchronous DRAM typical timing

|- style="line-height:130%"

!rowspan=2 colspan=2| ||colspan=2|PC-3200 <br>(DDR-400)||colspan=2|PC2-6400 <br>(DDR2-800)||colspan=2|PC3-12800 <br>(DDR3-1600)||rowspan=2|Description

|-

!cycles||time||cycles||time||cycles||time

|-

!rowspan=2|''t''_CL||Typicaltypical

|3||15&nbsp;ns||5||12.5&nbsp;ns||9||11.25&nbsp;ns

|rowspan=2 align=left|/CAS low to valid data out <br>(equivalent to ''t''_CAC)

|-

!fast

!Fast

|2||10&nbsp;ns||4||10&nbsp;ns||8||10&nbsp;ns

|-

!rowspan=2|''t''_RCD||Typicaltypical

|4||20&nbsp;ns||5||12.5&nbsp;ns||9||11.25&nbsp;ns

|rowspan=2 align=left|/RAS low to /CAS low time

|-

!fast

!Fast

|2||10&nbsp;ns||4||10&nbsp;ns||8||10&nbsp;ns

|-

!rowspan=2|''t''_RP||Typicaltypical

|4||20&nbsp;ns||5||12.5&nbsp;ns||9||11.25&nbsp;ns

|rowspan=2 align=left|/RAS precharge time <br>(minimum precharge to active time)

|-

!fast

!Fast

|2||10&nbsp;ns||4||10&nbsp;ns||8||10&nbsp;ns

|-

!rowspan=2|''t''_RAS||Typicaltypical

|8||40&nbsp;ns||16||40&nbsp;ns||27||33.75&nbsp;ns

|rowspan=2 align=left|Row active time <br>(minimum active to precharge time)

|-

!fast

!Fast

|5||25&nbsp;ns||12||30&nbsp;ns||24||30&nbsp;ns

|}