Latency oriented processor architecture: Difference between revisions

Revision as of 15:51, 29 January 2023

Latest revision as of 20:23, 6 June 2025

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===Instruction set architecture (ISA)===

{{Main|Instruction set}}

Most architectures today use shorter and simpler instructions, like the [[load/store architecture]], which help in optimizing the instruction pipeline for faster execution. Instructions are usually all of the same size which also helps in optimizing the instruction fetch logic. Such an ISA is called a [[Reduced instruction set computing|RISC]] architecture.<ref>{{cite conference|last1=Bhandarkar|first1=Dileep|last2=Clark|first2=Douglas W. |title=PerformanceProceedings fromof Architecture:the Comparingfourth ainternational RISCconference andon aArchitectural CISCsupport withfor Similarprogramming Hardwarelanguages and operating systems - ASPLOS-IV Organization|journalchapter=ProceedingsPerformance offrom thearchitecture: FourthComparing Internationala ConferenceRISC onand Architecturala SupportCISC forwith Programmingsimilar Languages andhardware Operatingorganization Systems|date=1 January 1991|pages=310–319|doi=10.1145/106972.107003|url=http://dl.acm.org/citation.cfm?id=107003&CFID=860927590&CFTOKEN=39315780|publisher=ACM|isbn=0897913809 |doi-access=free}}</ref>

===Instruction pipelining===