Serial Peripheral Interface: Difference between revisions

Revision as of 15:12, 11 March 2025

Revision as of 23:56, 8 June 2025

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| data_style = [[Full-duplex]] [[serial communication|serial]]

| daisy_chain = [[#Daisy chain configuration|Depends]] on devices

| manufacturer = variousVarious

| data_devices = [[#Multidrop configuration|Multidrop]] limited by slave selects. [[#Daisy chain configuration|Daisy chaining]] unlimited.

| data_bit_width = 1 bit (bidirectional)

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| maximum_current = Unspecified

| physical_connector = Unspecified

| design_date = Around early 1980s{{NoteTag|The earliest definitive mention of a "Serial Peripheral Interface" in bitsavers archives of Motorola manuals is from 1983 (see {{slink||Original definition}}). While some sources on the web allege that Motorola introduced SPI when 68000 was introduced in 1979, however many of those appear to be [[citogenesis]] or speculation, and Motorola's 1983 68000 manual has no mention of "Serial Peripheral Interface", so the alleged 1979 date doesn'tdoes not seem to be reliable information. Please only add a specific design_date if you have a definitive source from Motorola around then.}}

}}

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===Data transmission===

[[File:SPI 8-bit circular transfer.svg|upright=1.8|thumb|A typical hardware setup using two [[shift register]]s to form an inter-chip [[circular buffer]] ]]

To begin communication, the SPI master first selects a slave device by pulling its {{Overline|SS}} low. (Note: theThe bar above {{Overline|SS}} indicates it is an [[active low]] signal, so a low voltage means "selected", while a high voltage means "not selected")

If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.{{NoteTag|Some slaves require a falling edge of the {{Overline|Slave Select}} signal to initiate an action. An example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition.}}

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If a single slave device is used, its {{Overline|SS}} pin ''may'' be fixed to [[logic level|logic low]] if the slave permits it. With multiple slave devices, a [[#Multidrop configuration|multidrop configuration]] requires an independent {{Overline|SS}} signal from the master for each slave device, while a [[#Daisy chain configuration|daisy-chain configuration]] only requires one {{Overline|SS}} signal.

Every slave on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent [[Bus contention|contention]] on MISO, non-selected slaves must use [[Three-state logic|tristate]] output. Slaves that aren'tare not already tristate will need external tristate buffers to ensure this.<ref name="Better SPI Bus Design in 3 Steps" />

===Clock polarity and phase===

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*** Sampling occurs when SCLK transitions ''to'' its idle voltage level.

** Conversion between these two phases is non-trivial.

** Note: MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next bit's transmission cycle starts, so SPI master and slave devices may sample data at different points in that half cycle, for flexibility, despite the original specification.

===Mode numbers ===

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** Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than [[Parallel communication|parallel interfaces]]

*** At most one unique signal per device ({{Overline|SS}}); all others are shared

**** Note: theThe daisy-chain configuration doesn'tdoes not need more than one shared {{Overline|SS}}

** Typically lower power requirements than [[I²C]] or SMBus due to less circuitry (including pull up resistors)

** Single master means no [[bus arbitration]] (and associated failure modes) - unlike [[CAN-bus]]

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=== No slave select ===

Some devices don'tdo not use slave select, and instead manage protocol state machine entry/exit using other methods.

=== Connectors ===