Field-effect transistor: Difference between revisions

Revision as of 21:48, 1 June 2025

Revision as of 00:57, 11 June 2025

Line 3:

{{short description|Type of transistor}}

[[File:FET cross section.svg|thumb|300px|Cross-sectional view of a MOSFET type field-effect transistor, showing ''source'', ''gate'' and ''drain'' terminals, and insulating oxide layer.]]

The '''field-effect transistor''' ('''FET''') is a type of [[transistor]] that uses an [[electric field]] to control the [[Electric current|current]] through a [[semiconductor]]. It comes in two types: [[JFET|junction FET]] (JFET) and [[MOSFET|metal-oxide-semiconductor FET]] (MOSFET). FETs have three terminals: ''source'', ''gate'', and ''drain''. FETs control the current by the application of a [[voltage]] to the gate, which in turn alters the [[Electrical resistivity and conductivity|conductivity]] between the drain and source.

FETs are also known as '''unipolar transistors''' since they involve single-carrier-type operation. That is, FETs use either [[electron]]s (n-channel) or [[hole (semiconductor)|hole]]s (p-channel) as [[charge carrier]]s in their operation, but not both. Many different types of field effect transistors exist. Field effect transistors generally display very [[High impedance|high input impedance]] at low frequencies. The most widely used field-effect transistor is the [[MOSFET]] (metal–oxide–semiconductor field-effect transistor).

Line 15:

The first FET device to be successfully built was the [[JFET|junction field-effect transistor]] (JFET).<ref name="Lee"/> A JFET was first patented by [[Heinrich Welker]] in 1945.<ref>{{cite book |title=The Physics of Semiconductors|author=Grundmann, Marius|isbn=978-3-642-13884-3 |publisher=Springer-Verlag|year=2010}}</ref> The [[static induction transistor]] (SIT), a type of JFET with a short channel, was invented by Japanese engineers [[Jun-ichi Nishizawa]] and Y. Watanabe in 1950. Following Shockley's theoretical treatment on the JFET in 1952, a working practical JFET was built by [[George C. Dacey]] and [[Ian Munro Ross|Ian M. Ross]] in 1953.<ref name=sit>{{cite book|first=Jun-Ichi |last=Nishizawa|editor-first1=Roland|editor-last1=Sittig|editor-first2=P.|editor-last2=Roggwiller|publisher=Springer|chapter=Junction Field-Effect Devices|title=Semiconductor Devices for Power Conditioning|year=1982|pages=241–272|doi=10.1007/978-1-4684-7263-9_11|isbn=978-1-4684-7265-3}}</ref> However, the JFET still had issues affecting [[junction transistor]]s in general.<ref name="Moskowitz">{{cite book |last1=Moskowitz |first1=Sanford L. |title=Advanced Materials Innovation: Managing Global Technology in the 21st century |date=2016 |publisher=[[John Wiley & Sons]] |isbn=978-0-470-50892-3 |page=168 |url=https://books.google.com/books?id=2STRDAAAQBAJ&pg=PA168}}</ref> Junction transistors were relatively bulky devices that were difficult to manufacture on a [[mass-production]] basis, which limited them to a number of specialised applications. The insulated-gate field-effect transistor (IGFET) was theorized as a potential alternative to junction transistors, but researchers were unable to build working IGFETs, largely due to the troublesome surface state barrier that prevented the external [[electric field]] from penetrating into the material.<ref name="Moskowitz"/> By the mid-1950s, researchers had largely given up on the FET concept, and instead focused on [[bipolar junction transistor]] (BJT) technology.<ref name="triumph">{{cite web |title=The Foundation of Today's Digital World: The Triumph of the MOS Transistor |url=https://www.youtube.com/watch?v=q6fBEjf9WPw |publisher=[[Computer History Museum]] |access-date=21 July 2019 |date=13 July 2010}}</ref>

The foundations of MOSFET technology were laid down by the work of [[William Shockley]], [[John Bardeen]] and [[Walter Brattain]]. Shockley independently envisioned the FET concept in 1945, but he was unable to build a working device. The next year Bardeen explained his failure in terms of [[surface states]]. Bardeen applied the theory of surface states on semiconductors (previous work on surface states was done by Shockley in 1939 and [[Igor Tamm]] in 1932) and realized that the external field was blocked at the surface because of extra electrons which are drawn to the semiconductor surface. Electrons become trapped in those localized states forming an inversion layer. Bardeen's hypothesis marked the birth of [[Surface_science#Physics|surface physics]]. Bardeen then decided to make use of an inversion layer instead of the very thin layer of semiconductor which Shockley had envisioned in his FET designs. Based on his theory, in 1948 Bardeen patented the progenitor of MOSFET, an insulated-gate FET (IGFET) with an inversion layer. The inversion layer confines the flow of minority carriers, increasing modulation and conductivity, although its electron transport depends on the gate's insulator or quality of oxide if used as an insulator, deposited above the inversion layer. Bardeen's patent as well as the concept of an inversion layer forms the basis of CMOS technology today. In 1976 Shockley described Bardeen's surface state hypothesis "as one of the most significant research ideas in the semiconductor program".<ref name="b1">{{cite book | author=Howard R. Duff | title=AIP Conference Proceedings | chapter=John Bardeen and transistor physics | date=2001 | volume=550 | pages=3–32 | doi=10.1063/1.1354371 | doi-access=free }}</ref>

After Bardeen's surface state theory the trio tried to overcome the effect of surface states. In late 1947, Robert Gibney and Brattain suggested the use of electrolyte placed between metal and semiconductor to overcome the effects of surface states. Their FET device worked, but amplification was poor. Bardeen went further and suggested to rather focus on the conductivity of the inversion layer. Further experiments led them to replace electrolyte with a solid oxide layer in the hope of getting better results. Their goal was to penetrate the oxide layer and get to the inversion layer. However, Bardeen suggested they switch from [[silicon]] to [[germanium]] and in the process their oxide got inadvertently washed off. They stumbled upon a completely different transistor, the [[point-contact transistor]]. [[Lillian Hoddeson]] argues that "had Brattain and Bardeen been working with silicon instead of germanium they would have stumbled across a successful field effect transistor".<ref name="b1" /><ref name="Camezind">{{cite book | author=Hans Camenzind | author-link=Hans Camenzind | title=Designing Analog Chips | date=2005 | url=http://www.designinganalogchips.com/}}</ref><ref>{{cite book | title=ULSI Science and Technology/1997 | url= https://books.google.com/books?id=I8_O1anzKpsC | date=1997 |

Line 28:

===Metal-oxide-semiconductor FET (MOSFET)===

{{Main|MOSFET}}

[[File:1957(Figure_9)-Gate_oxide_transistor_by_Frosch_and_Derrick.png|thumb|310x310px|1957, Diagramdiagram of one of the SiO2SiO₂ transistor devices made by Frosch and Derrick<ref name=":1"/>]]

In 1955, [[Carl Frosch]] and Lincoln Derrick accidentally grew a layer of silicon dioxide over the silicon wafer, for which they observed [[surface passivation]] effects.<ref name=":0">{{Cite journal |last1=Huff |first1=Howard |last2=Riordan |first2=Michael |date=2007-09-01 |title=Frosch and Derick: Fifty Years Later (Foreword) |url=https://iopscience.iop.org/article/10.1149/2.F02073IF |journal=The Electrochemical Society Interface |volume=16 |issue=3 |pages=29 |doi=10.1149/2.F02073IF |issn=1064-8208}}</ref><ref name="auto"/> By 1957 Frosch and Derrick, using masking and predeposition, were able to manufacture silicon dioxide transistors and showed that silicon dioxide insulated, protected silicon wafers and prevented dopants from diffusing into the wafer.<ref name=":0" /><ref name=":1"/> J.R. Ligenza and W.G. Spitzer studied the mechanism of thermally grown oxides and fabricated a high quality Si/[[Silicon dioxide|SiO₂]] stack in 1960.<ref>{{Cite journal |last1=Ligenza |first1=J. R. |last2=Spitzer |first2=W. G. |date=1960-07-01 |title=The mechanisms for silicon oxidation in steam and oxygen |url=https://linkinghub.elsevier.com/retrieve/pii/0022369760902195 |journal=Journal of Physics and Chemistry of Solids |volume=14 |pages=131–136 |doi=10.1016/0022-3697(60)90219-5 |bibcode=1960JPCS...14..131L |issn=0022-3697}}</ref><ref name="Deal">{{cite book |last1=Deal |first1=Bruce E. |title=Silicon materials science and technology |date=1998 |publisher=[[The Electrochemical Society]] |isbn=978-1566771931 |page=183 |chapter=Highlights Of Silicon Thermal Oxidation Technology |chapter-url=https://books.google.com/books?id=cr8FPGkiRS0C&pg=PA183}}</ref><ref>{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer Science & Business Media |isbn=978-3540342588 |page=322}}</ref>

Line 42:

The FET's three terminals are:<ref name=millman>{{cite book|author=Jacob Millman|title=Electronic devices and circuits|year=1985|pages=384–385|publisher=McGraw-Hill|___location=Singapore|isbn=978-0-07-085505-2}}</ref>

#sourceSource (S), through which the carriers enter the channel. Conventionally, current entering the channel at S is designated by I_S.

#drainDrain (D), through which the carriers leave the channel. Conventionally, current leaving the channel at D is designated by I_D. Drain-to-source voltage is V_DS.

#gateGate (G), the terminal that modulates the channel conductivity. By applying voltage to G, one can control I_D.

==More about terminals==

[[File:Lateral mosfet.svg|thumbnail|Cross section of an n-type MOSFET]]

All FETs have ''source'', ''drain'', and ''gate'' terminals that correspond roughly to the ''emitter'', ''collector'', and ''base'' of [[bipolar junction transistor|BJT]]s. Most FETs have a fourth terminal called the ''body'', ''base'', ''bulk'', or ''[[substrate (electronics)|substrate]].'' This fourth terminal serves to [[biasing (electronics)|bias]] the transistor into operation; it is rare to make non-trivial use of the body terminal in circuit designs, but its presence is important when setting up the [[integrated circuit layout|physical layout]] of an [[integrated circuit]]. The size of the gate, length ''L'' in the diagram, is the distance between source and drain. The ''width'' is the extension of the transistor, in the direction perpendicular to the cross section in the diagram (i.e., into/out of the screen). Typically the width is much larger than the length of the gate. A gate length of 1&nbsp;μm limits the upper frequency to about 5&nbsp;GHz, 0.2&nbsp;μm to about 30&nbsp;GHz.

The names of the terminals refer to their functions. The gate terminal may be thought of as controlling the opening and closing of a physical gate. This gate permits electrons to flow through or blocks their passage by creating or eliminating a channel between the source and drain. Electron-flow from the source terminal towards the drain terminal is influenced by an applied voltage. The body simply refers to the bulk of the semiconductor in which the gate, source and drain lie. Usually the body terminal is connected to the highest or lowest voltage within the circuit, depending on the type of the FET. The body terminal and the source terminal are sometimes connected together since the source is often connected to the highest or lowest voltage within the circuit, although there are several uses of FETs which do not have such a configuration, such as [[transmission gate]]s and [[cascode]] circuits.

Unlike BJTs, the vast majority of FETs are electrically symmetrical. The source and drain terminals can thus be interchanged in practical circuits with no change in operating characteristics or function. This can be confusing when FET's appear to be connected "backwards" in schematic diagrams and circuits because the physical orientation of the FET was decided for other reasons, such as printed circuit layout considerations.

===Effect of gate voltage on current===

Line 105:

**The DGMOSFET ([[dual-gate MOSFET]]) or DGMOS, a MOSFET with two insulated gates.

**The IGBT ([[insulated-gate bipolar transistor]]) is a device for power control. It has a structure akin to a MOSFET coupled with a bipolar-like main conduction channel. These are commonly used for the 200–3000 V drain-to-source voltage range of operation. [[Power MOSFET]]s are still the device of choice for drain-to-source voltages of 1 to 200 V.

**The JLNT ([[Junctionlessjunctionless nanowire transistor]]) is a type of Fieldfield-effect transistor (FET) which channel is one or multiple nanowires and does not present any junction.

**The MNOS ([[metal–nitride–oxide–semiconductor transistor]]) utilizes a nitride-oxide layer [[Electrical insulation|insulator]] between the gate and the body.

**The [[ISFET]] (ion-sensitive field-effect transistor) can be used to measure ion concentrations in a solution; when the ion concentration (such as H⁺, see [[pH electrode]]) changes, the current through the transistor will change accordingly.

Line 130:

*The GFET is a highly sensitive graphene-based field effect transistor used as [[biosensor]]s and [[Sensor#Chemical sensor|chemical sensors]]. Due to the 2 dimensional structure of graphene, along with its physical properties, GFETs offer increased sensitivity, and reduced instances of 'false positives' in sensing applications<ref>{{cite web|author=Miklos, Bolza|title=What Are Graphene Field Effect Transistors (GFETs)?|url=https://www.graphenea.com/pages/what-are-graphene-field-effect-transistors-gfets|website=Graphenea|access-date=14 January 2019}}</ref>

*The [[Fe FET]] uses a [[ferroelectric]] between the gate, allowing the transistor to retain its state in the absence of bias - such devices may have application as [[non-volatile memory]].

* VTFET, or [[Verticalvertical-Transporttransport Fieldfield-Effecteffect Transistortransistor]], IBM's 2021 modification of [[finFETFinFET]] to allow higher density and lower power.<ref>{{Cite web|url=https://www.marktechpost.com/2021/12/21/ibm-research-unveils-vtfet-a-revolutionary-new-chip-architecture-which-is-two-times-the-performance-finfet/|title=IBM Research Unveils 'VTFET': A Revolutionary New Chip Architecture Which is Two Times the Performance finFET|first=Prathamesh|last=Ingle|date=December 21, 2021}}</ref>

==Advantages==