Transaction-level modeling: Difference between revisions

Revision as of 14:25, 20 June 2025

Revision as of 00:58, 23 June 2025

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The methodology has become essential in modern [[electronic design automation]] (EDA) flows, particularly for creating [[virtual platform]]s that enable early [[software development]] and system validation before hardware implementation is complete.<ref name="Virtual_Platforms">{{cite conference |title=Virtual Platforms in System-Level Design |author=Schirner, Gunar |conference=Design Automation Conference |year=2013 |pages=804-809 |doi=10.1145/2463209.2488885}}</ref> TLM models serve as executable specifications that bridge the gap between high-level system requirements and detailed hardware implementations. TLMs are used for [[high-level synthesis]] of [[register-transfer level]] (RTL) models for a lower-level modelling and implementation of system components. RTL is usually represented by a [[hardware description language]] source code (e.g. [[VHDL]], [[SystemC]], [[Verilog]]).{{r|TVLSIHB-2007|pp=1955-1957}}

==Background and Historyhistory==

===Early Developmentdevelopment (1990s-2000s)===

Transaction-level Level Modelingmodeling emerged in the late 1990s and early 2000s as a direct response to the increasing complexity of [[System-on-a-chip|system-on-chip]] designs and the limitations of traditional [[Register-transfer level|register-transfer level]] (RTL) modeling for system-level verification and software development.<ref name="Gajski_ESL">{{cite book |title=SpecC: Specification Language and Methodology |author=Gajski, Daniel D. |publisher=Kluwer Academic Publishers |year=2000 |isbn=978-0-7923-7822-5}}</ref> The semiconductor industry was experiencing a widening disparity between design complexity and designer productivity.<ref name="ITRS_Design">{{cite report |title=International Technology Roadmap for Semiconductors: Design |publisher=Semiconductor Industry Association |year=1999 |url=http://www.itrs.net/}}</ref>

The foundational concepts of TLM were developed simultaneously by several research groups and companies. [[Cadence Design Systems]] introduced early transaction-level concepts in their [[SpecC]] language in the mid-1990s,<ref name="SpecC_Origins">{{cite conference |title=SpecC: A Design Language for System Level Design |author=Gajski, Daniel D. |conference=Design Automation Conference |year=1997 |pages=464-469 |doi=10.1145/266021.266138}}</ref> while [[Synopsys]] developed similar concepts in their [[SystemC]] methodology starting in 1999.<ref name="SystemC_History">{{cite journal |title=SystemC: Past, Present, and Future |author=Grötker, Thorsten |journal=IEEE Design & Test |volume=20 |issue=6 |pages=72-77 |year=2003 |doi=10.1109/MDT.2003.1246169}}</ref>

In 2000, Thorsten Grötker, R&D Managermanager at [[Synopsys]] was preparing a presentation on the communication mechanism in what was to become the [[SystemC]] 2.0 standard, and referred to it as "transaction-based modeling". Gilles Baillieu, then a corporate application engineer at Synopsys, insisted that the new term had to contain "level", as in "[[register-transfer level]]" or "behavioral level". The fact that TLM does not denote a single level of abstraction but rather a modeling technique didn't make him change his mind. It had to be "level" in order to make it stick. So it became "TLM".{{Citation needed|date=March 2008}}

===SystemC and OSCI Formationformation===

The development of [[SystemC]] proved crucial to TLM's adoption. SystemC was initially developed by [[Synopsys]] in 1999 as a [[C++]]-based system-level modeling language.<ref name="SystemC_Announcement">{{cite news |title=Synopsys Introduces SystemC for System-Level Design |newspaper=EE Times |date=1999-10-04 |url=https://www.eetimes.com/synopsys-introduces-systemc/}}</ref> In 2000, the [[Open SystemC Initiative]] (OSCI) was formed as an independent consortium to develop and promote SystemC as an open standard.<ref name="OSCI_Formation">{{cite press release |title=Open SystemC Initiative Formed to Advance System-Level Design |publisher=Open SystemC Initiative |date=2000-09-12}}</ref> Founding members included [[Synopsys]], [[Cadence Design Systems]], [[CoWare]], and several major semiconductor companies including [[ARM Holdings]], [[Infineon Technologies]], and [[STMicroelectronics]].<ref name="OSCI_Members">{{cite web |url=https://www.accellera.org/about/history |title=Accellera History |publisher=Accellera Systems Initiative |access-date=2024-01-15}}</ref> The organization developed the OSCI simulator for open use and distribution.

Since those early days SystemC has been adopted as the language of choice for high level synthesis, connecting the design modeling and virtual prototype application domains with the functional verification and automated path gate level implementation. This offers project teams the ability to produce one model for multiple purposes. At the 2010 DVCon event, OSCI produced a specification of the first synthesizable subset of SystemC for industry standardization.

===TLM 1.0 Standardizationstandardization (2005)===

The first standardized TLM methodology, known as '''TLM-1.0''', was released by OSCI in 2005.<ref name="TLM_1_0_Release">{{cite press release |title=OSCI Releases Transaction Level Modeling Standard |publisher=Open SystemC Initiative |date=2005-06-15}}</ref> TLM-1.0 introduced fundamental concepts including:

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The TLM-1.0 standard was primarily focused on functional modeling and provided limited support for detailed timing analysis.<ref name="Ghenassia_TLM_1">{{cite book |title=Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems |editor=Ghenassia, Frank |publisher=Springer |year=2005 |chapter=TLM-1.0 Standard |pages=87-124 |isbn=978-0-387-26233-4}}</ref>

===TLM 2.0 Evolutionevolution and IEEE Standardizationstandardization (2008-2011)===

'''TLM-2.0''', released in 2008, represented a major advancement in transaction-level modeling methodology.<ref name="TLM_2_0_Release">{{cite press release |title=OSCI Releases TLM-2.0 Standard for Transaction-Level Modeling |publisher=Open SystemC Initiative |date=2008-06-10}}</ref> The new standard introduced several key innovations:

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TLM-2.0 was subsequently incorporated into the [[IEEE]] 1666-2011 standard for SystemC, providing official recognition and broader industry acceptance.<ref name="IEEE_1666_2011">{{cite standard |title=IEEE Standard for Standard SystemC Language Reference Manual |standard=IEEE Std 1666-2011 |publisher=IEEE |year=2012 |doi=10.1109/IEEESTD.2012.6134619}}</ref>

===Industry Adoptionadoption and Commercialcommercial Toolstools===

By the mid-2000s, major [[Electronic Design Automation|EDA]] companies began incorporating TLM support into their commercial tools. [[Mentor Graphics]] (now [[Siemens EDA]]) introduced TLM support in their ModelSim simulator in 2004,<ref name="ModelSim_TLM">{{cite news |title=Mentor Graphics Adds SystemC TLM to ModelSim |newspaper=EE Times |date=2004-03-15}}</ref> followed by [[Cadence Design Systems]] with their Incisive platform in 2005.<ref name="Cadence_TLM">{{cite press release |title=Cadence Introduces Transaction-Level Modeling Flow |publisher=Cadence Design Systems |date=2005-09-12}}</ref>

Virtual platform companies such as [[CoWare]] (acquired by Synopsys in 2010),<ref name="Synopsys_CoWare">{{cite news |title=Synopsys Acquires CoWare for Virtual Prototyping |newspaper=EE Times |date=2010-02-22}}</ref> Vast Systems (acquired by Synopsys in 2007), and VaST Systems Technology contributed significantly to TLM's commercial adoption by providing high-performance virtual platforms based on TLM methodology.<ref name="Virtual_Platform_Market">{{cite report |title=Virtual Prototyping Market Analysis |publisher=Gary Smith EDA |year=2010}}</ref>

===Modern Developmentsdevelopments (2010s-Presentpresent)===

The 2010s saw TLM become standard practice in the semiconductor industry, particularly for [[ARM architecture|ARM]]-based SoC design. [[ARM Holdings]] released comprehensive TLM models of their processor architectures, including [[ARM Cortex-A]] and [[ARM Cortex-M]] series processors.<ref name="ARM_TLM_Models">{{cite white paper |title=ARM Fast Models: System-Level Modeling for Software Development |publisher=ARM Holdings |year=2012}}</ref>

The rise of [[artificial intelligence]] and [[machine learning]] accelerators in the late 2010s created new demands for TLM modeling, leading to specialized libraries and methodologies for modeling [[neural processing unit]]s and other AI hardware.<ref name="AI_TLM">{{cite conference |title=Transaction-Level Modeling for AI Accelerator Design |author=Chen, Li |conference=Design Automation Conference |year=2019 |pages=1-6 |doi=10.1145/3316781.3317788}}</ref>