Systolic array: Difference between revisions

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Implementations: some older ones, Warp & iWarp already mentioned above. Not sure if they should be repeated here or not.
Implementations: While it was marketed that it could be used like this if networked (via its 6 ports) I've not found much evidence of actual use like that.
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* Inmos [[Transputer]]<ref name="HSP">"Systolic Arrays" in *Handbook of Signal Processing Systems* (3rd ed.), 2018
https://link.springer.com/chapter/10.1007/978-3-319-91734-4_26</ref>
* [[TMS320]]C4x<ref name="HSP"/><ref>Parallel Processing with the TMS320C4x, 1994 https://www.ti.com/lit/an/spra031/spra031.pdf?ts=1752134833800</ref>
* [[Cisco]] PXF network processor is internally organized as systolic array.<ref>{{cite web|title=Cisco 10000 Series Router Performance Routing Engine Installation|url=https://www.cisco.com/en/US/products/hw/routers/ps133/prod_installation_guide09186a0080525aba.html#wp48065|access-date=3 August 2020}}</ref>
* Google’s [[Tensor Processing Unit|TPU]] is also designed around a systolic array.