{{See also|#Operations to read a data bit from a DRAM storage cell}}DRAM are [[Volatile memory|volatile]] memories that means they require memory cell to be periodically refreshed so to retain information. Cells failing to satisfy refresh specification can result in bit-flips thus corrupting the stored data. Additional errors may arise during the write operation, caused by incomplete charging of the storage capacitor or the presence of defects in the memory array that prevent this operation to be carried out correctly.<ref>{{Cite journal |last=Kang |first=Uksong |date=2014 |title=Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling |url=https://www.semanticscholar.org/paper/Co-Architecting-Controllers-and-DRAM-to-Enhance-Kang-Yu/e762b1b654798cec0fb9d6000c7f7c777ac0689f |journal=The Memory Forum 2014}}</ref>
{{See also|#Operations to read a data bit from a DRAM storage cell}}
DynamicData memory,corruption bymay definition,arise requiresdue periodicto refresh.different Furthermore, reading dynamic memory is a destructive operation, requiring a recharge of the storage cells in the row that has been readsources. If these processes are imperfect, a readOne operationsource can causebe [[softdisturbance error]]s.errors Incaused particular,by there is a risk that some charge canthe leakinterference between nearbyneighboring cells,causingthat thesome refresh or read of one row to cause a ''disturbance error''researchers in an2014 adjacentpointed orout evencould nearbybe row.used Theas awarenessa ofcomputer disturbanceexploit, errorsthis datestechnique backwas todubbed the first commercially available DRAM in the early 1970s (theas [[Intelrow 1103hammer]]). Despite the mitigation techniques employed by manufacturers, commercial researchers proved in a 2014 analysis that commercially available [[DDR3]] DRAM chips manufactured in 2012 and 2013 are susceptible to disturbance errors.<ref>{{cite web | url = http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_kim_talk_isca14.pdf | title = Flipping Bits in Memory Without Accessing Them: DRAM Disturbance Errors | date = June 24, 2014 | access-date = March 10, 2015 | author1=Yoongu Kim |author2=Ross Daly |author3=Jeremie Kim |author4=Chris Fallin |author5=Ji Hye Lee |author6=Donghyuk Lee |author7=Chris Wilkerson |author8=Konrad Lai |author9=Onur Mutlu |date=June website24, 2014 |title=Flipping Bits in Memory Without Accessing Them: DRAM Disturbance Errors |url=http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_kim_talk_isca14.pdf |url-status=live |archive-url=https://web.archive.org/web/20150326080426/http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_kim_talk_isca14.pdf |archive-date=2015-03-26 |access-date=March 10, 2015 |website=ece.cmu.edu}}</ref> TheOther associatedsources sideof effecterrors thatinclude ledexposure to observedionizing bitradiation flipscausing has[[Single-event beenupset|single-event-upset]], dubbedand the presence of defects in the memory cell responsible for unpredictable instabilities in the leakage current discharging the storage capacitor, a phenomena also known as ''[[rowvariable hammerretention time]]'' (VRT). <ref>{{Cite journal |last=Restle |last2=Park |last3=Lloyd |date=1992 |title=DRAM variable retention time |url=https://ieeexplore.ieee.org/document/307481/ |journal=1992 International Technical Digest on Electron Devices Meeting |pages=807–810 |doi=10.1109/IEDM.1992.307481}}</ref>
To mitigate these issues, device manufacturers modified the design incorporating error correction strategies, such as [[Variable retention time#Screening and in-DRAM ECC|in-DRAM ECC]] to mitigate VRT, and [[Row hammer#Mitigation|target-row-refresh]] (TRR) and other technique to manage row hammer. <ref>{{Citation |last=Kim |first=Jumin |title=Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads |date=2025-07-08 |url=http://arxiv.org/abs/2507.05556 |access-date=2025-07-11 |publisher=arXiv |doi=10.48550/arXiv.2507.05556 |id=arXiv:2507.05556 |last2=Baek |first2=Seungmin |last3=Wi |first3=Minbok |last4=Nam |first4=Hwayong |last5=Kim |first5=Michael Jaemin |last6=Lee |first6=Sukhan |last7=Sohn |first7=Kyomin |last8=Ahn |first8=Jung Ho}}</ref>
