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[[File:Simple NIC and cores architecture.png|thumb|upright=1.7|Simple graph showing the path receiving packets need to travel to reach the cores' queues]]
For this reason many techniques, both in hardware and in software, are leveraged in order to distribute the incoming load of packets across the cores of the [[Central processing unit|processor]].
As shown by the figure beside, packets coming into the [[Network_interface_controller|network interface card (NIC)]] are processed and loaded to the receiving queues managed by the cores (which are usually implemented as [[Circular buffer|ring buffers]] within the [[User space and kernel space|kernel space]]).
The main objective is being able to leverage all the cores available within the [[Central processing unit|CPU]] to process incoming packets, while also improving performances like [[Latency (engineering)|latency]] and [[Network throughput|throughput]].<ref name="RSS kernel linux docs">{{Cite web|title=RSS kernel linux docs|url=https://www.kernel.org/doc/html/v5.1/networking/scaling.html#rss-receive-side-scaling|access-date=2025-07-08|website=kernel.org|publisher=The Linux Kernel documentation|language=en-US}}</ref><ref name="RSS overview by microsoft">{{Cite web|title=RSS overview by microsoft|url=https://learn.microsoft.com/en-us/windows-hardware/drivers/network/introduction-to-receive-side-scaling|access-date=2025-07-08|website=learn.microsoft.com|language=en-US}}</ref><ref>{{Cite journal |last=Wu |first=Wenji |last2=DeMar |first2=Phil |last3=Crawford |first3=Matt |date=2011-02-01 |title=Why Can Some Advanced Ethernet NICs Cause Packet Reordering? |url=https://ieeexplore.ieee.org/document/5673999/ |journal=IEEE Communications Letters |doi=10.1109/LCOMM.2011.122010.102022 |issn=1558-2558}}</ref>
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