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By 2024 SCI Semiconductors announced ICENI,<ref name=iceni>{{cite web |last1=Flaherty |first1=Nick |date=23 October 2024 |title=First CHERI RISC-V embedded chip and Early Access Programme |url=https://www.eenewseurope.com/en/first-cheri-risc-v-embedded-chip-and-early-access-programme/ |access-date=11 January 2025 |publisher=eeNews Europe}}</ref> a CHERIoT-compatible chip designed specifically for secure embedded systems. Codasip is actively developing a Linux kernel implementation for the RISC-V architecture.<ref>{{cite web |url=https://codasip.com/press-release/2024/10/21/codasip-enables-secure-linux-by-donating-cheri-risc-v-sdk-to-the-cheri-alliance/ |title=Codasip enables secure Linux by donating CHERI RISC-V SDK to the CHERI Alliance |publisher=Codasip |date=21 October 2024 |access-date=20 January 2025}}</ref> The CHERI Alliance, a non-profit organisation based in Cambridge, UK, was established to promote the adoption of CHERI technology and its integration into secure digital products and systems, including Google as a founding member.<ref name="cheri-alliance-launched"/>
In 2025 Wyvern Global's Semiconductors Division announced WARP <ref name=WARP>{{cite web |date=11 July 2025 |title=Wyvern Advanced RISC-V Processor |url=https://warp.wyvern.global/ |access-date=11 July 2025 |publisher=Wyvern Global}}</ref>, the first commercially available CHERI-BSD native RISC-V chipset built from the ground up with CHERI in mind, and announced an OEM adoption programme under the same name for existing manufacturer's to integrate the technology into their existing boards using the WARP chipset. They have also pledged adoption of CHERI into all of their existing products and services end-to-end going forward and joined the CHERI alliance C.I.C <ref name=
==References==
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