Flash memory: Difference between revisions

Revision as of 20:17, 10 July 2025

Revision as of 13:26, 14 July 2025

Line 6:

{{Memory types}}

'''Flash memory''' is an [[Integrated circuit|electronic]] [[Non-volatile memory|non-volatile]] [[computer memory]] [[storage medium]] that can be electrically erased and reprogrammed. The two main types of flash memory, '''NOR flash''' and '''NAND flash''', are named for the [[NOR gate|NOR]] and [[NAND gate|NAND]] [[logic gategates]]s. Both use the same cell design, consisting of [[floating-gate MOSFET]]s. They differ at the circuit level, depending on whether the state of the bit line or word lines is pulled high or low; in NAND flash, the relationship between the bit line and the word lines resembles a NAND gate; in NOR flash, it resembles a NOR gate.

Flash memory, a type of [[floating-gate]] memory, was invented by [[Fujio Masuoka]] at [[Toshiba]] in 1980 and is based on [[EEPROM]] technology. Toshiba began marketing flash memory in 1987.<ref name=":0" /> [[EPROM]]s had to be erased completely before they could be rewritten. NAND flash memory, however, may be erased, written, and read in blocks (or pages), which generally are much smaller than the entire device. NOR flash memory allows a single [[machine word]] to be written{{snd}} to an erased ___location{{snd}} or read independently. A flash memory device typically consists of one or more flash [[memory chip]]s (each holding many flash memory cells), along with a separate [[flash memory controller]] chip.

The NAND type is found mainly in [[memory card]]s, [[USB flash drive]]s, [[solid-state drive]]s (those produced since 2009), [[feature phone]]s, [[smartphone]]s, and similar products, for general storage and transfer of data. NAND or NOR flash memory is also often used to store configuration data in digital products, a task previously made possible by EEPROM or battery-powered [[static RAM]]. A key disadvantage of flash memory is that it can endure only a relatively small number of write cycles in a specific block.<ref name="flashstorage-2015">{{Cite news |date=30 March 2015 |title=A Flash Storage Technical and Economic Primer |work=FlashStorage.com |url=http://www.flashstorage.com/flash-storage-technical-economic-primer/ |url-status=dead |archive-url=https://web.archive.org/web/20150720220844/http://www.flashstorage.com/flash-storage-technical-economic-primer/ |archive-date=20 July 2015 }}</ref>

Line 63:

[[3D integrated circuit]] (3D IC) technology stacks [[integrated circuit]] (IC) chips vertically into a single 3D IC package.<ref name="James"/> Toshiba introduced 3D IC technology to NAND flash memory in April 2007, when they debuted a 16{{nbsp}}[[Gibibyte|GB]] eMMC compliant (product number THGAM0G7D8DBAI6, often abbreviated THGAM on consumer websites) embedded NAND flash memory package, which was manufactured with eight stacked 2{{nbsp}}GB NAND flash chips.<ref name="toshiba2007"/> In September 2007, [[Hynix Semiconductor]] (now [[SK Hynix]]) introduced 24-layer 3D IC technology, with a 16{{nbsp}}GB flash memory package that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.<ref name="hynix2007"/> Toshiba also used an eight-layer 3D IC for their 32{{nbsp}}GB THGBM flash package and in 2008.<ref name="toshiba2008"/> In 2010, Toshiba used a 16-layer 3D IC for their 128{{nbsp}}GB THGBM2 flash package, which was manufactured with 16 stacked 8{{nbsp}}GB chips.<ref name="toshiba2010"/> In the 2010s, 3D ICs came into widespread commercial use for NAND flash memory in [[mobile devices]].<ref name="James"/>

In 2016, Micron and Intel introduced a technology known as CMOS Under the Array/CMOS Under Array (CUA), Core over Periphery (COP), Periphery Under Cell (PUA), or Xtacking,<ref>{{Cite web|url=https://www.theregister.com/2018/08/06/china_aims_to_build_dramspeed_flash/|title=NAND we'll send foreign tech packing, says China of Xtacking: DRAM-speed... but light on layer-stacking|first=Chris|last=Mellor|website=www.theregister.com}}</ref> in which the control circuitry for the flash memory is placed under or above the flash memory cell array. This has allowed for an increase in the number of planes or sections a flash memory chip has, increasing from two planes to four, without increasing the area dedicated to the control or periphery circuitry. This increases the number of IO operations per flash chip or die, but it also introduces challenges when building capacitors for charge pumps used to write to the flash memory.<ref name="auto8">{{Cite web|url=https://www.anandtech.com/show/16491/flash-memory-at-isscc-2021|title=2021 NAND Flash Updates from ISSCC: The Leaning Towers of TLC and QLC|first=Billy|last=Tallis|website=www.anandtech.com}}</ref><ref>{{Cite news|url=https://www.theregister.com/2018/11/05/sk_hynix_96_layer_flash_chip/|title=What the PUC: SK Hynix next to join big boys in 96-layer 3D NAND land|first=Chris|last=Mellor|website=www.theregister.com}}</ref><ref>{{Cite news|url=https://www.theregister.com/2016/02/22/microns_journey_into_the_depths_of_nonvolatility/|title=Look who's avoided getting chatty about XPoint again. Micron... let's get non-volatile|first=Chris|last=Mellor|website=www.theregister.com}}</ref> Some flash dies have as many as 6 planes.<ref>{{Cite web |last=Alcorn |first=Paul |date=2022-07-26 |title=Micron Takes Lead With 232-Layer NAND Flash, up to 2TB per Chip Package |url=https://www.tomshardware.com/news/micron-takes-lead-with-232-layer-nand-up-to-2tb-per-chip-package |access-date=2024-05-31 |website=Tom's Hardware |language=en}}</ref>

As of August 2017, microSD cards with a capacity up to 400 [[gigabyte|GB]] (400 billion bytes) were available.<ref name="sandisk-20170831">{{Cite press release |date=31 August 2017 |title=Western Digital Breaks Boundaries with World's Highest-Capacity microSD Card |url=https://www.sandisk.com/about/media-center/press-releases/2017/western-digital-breaks-boundaries-with-worlds-highest-capacity-microsd-card |url-status=dead |archive-url=https://web.archive.org/web/20170901035345/https://www.sandisk.com/about/media-center/press-releases/2017/western-digital-breaks-boundaries-with-worlds-highest-capacity-microsd-card |archive-date=1 September 2017 |access-date=2 September 2017 |publisher=[[SanDisk]] |place=Berlin }}</ref><ref name="forbes-20170831">{{Cite magazine |last=Bradley |first=Tony |date=31 August 2017 |title=Expand Your Mobile Storage With New 400GB microSD Card From SanDisk |url=https://www.forbes.com/sites/tonybradley/2017/08/31/expand-your-mobile-storage-with-new-400gb-microsd-card-from-sandisk |url-status=live |magazine=[[Forbes]] |archive-url=https://web.archive.org/web/20170901064146/https://www.forbes.com/sites/tonybradley/2017/08/31/expand-your-mobile-storage-with-new-400gb-microsd-card-from-sandisk/ |archive-date=1 September 2017 |access-date=2 September 2017 }}</ref> Samsung combined 3D IC chip stacking with its 3D V-NAND and TLC technologies to manufacture its 512{{nbsp}}GB KLUFG8R1EM flash memory package with eight stacked 64-layer V-NAND chips.<ref name="anandtech-20171205" /> In 2019, Samsung produced a 1024{{nbsp}}[[Gigabyte|GB]] flash package, with eight stacked 96-layer V-NAND package and with QLC technology.<ref name="electronicsweekly-samsung"/><ref name="anandtech-samsung-2018"/>

In 2025, researchers announced experimental success with a device a 400-picosecond write time.<ref>{{Cite web |last=Shaikh |first=Kaif |title=China scientists develop flash memory 10,000× faster than current tech |url=https://interestingengineering.com/innovation/china-worlds-fastest-flash-memory-device?group=test_b |access-date=2025-04-20 |website=Interesting Engineering |language=en}}</ref>

==Principles of operation==

Line 261:

NOR and NAND flash differ in two important ways:

* The connections of the individual memory cells are different.<ref>{{Cite book|url=https://books.google.com/books?id=vaq11vKwo_kC&dq=nor+flash+nand+flash&pg=PA3|title=Inside NAND Flash Memories|first1=Rino|last1=Micheloni|first2=Luca|last2=Crippa|first3=Alessia|last3=Marelli|date=27 July 2010|publisher=Springer Science & Business Media|isbn=9789048194315 |via=Google Books}}</ref>

* The interface provided for reading and writing the memory is different; NOR allows [[random access]]<ref>{{cite book | url=https://books.google.com/books?id=abfBAAAAQBAJ&dq=nor+random+access&pg=PA35 | title=Flash Memories: Economic Principles of Performance, Cost and Reliability Optimization | isbn=978-94-007-6082-0 | last1=Richter | first1=Detlev | date=12 September 2013 | publisher=Springer }}</ref> as it can be either byte-addressable or word-addressable, with words being for example 32 bits long,<ref name="factsonfile">{{Cite book |last1=Daintith |first1=John |last2=Wright |first2=Edmund |url=https://books.google.com/books?id=9Q9XNh716ikC&dq=nor+byte+addressable&pg=PA123 |title=The Facts on File Dictionary of Computer Science |date=14 May 2014 |publisher=Infobase Publishing |isbn=9781438109398 |via=Google Books }}</ref><ref>{{Cite book|url=https://books.google.com/books?id=VDkPEAAAQBAJ&dq=nor+byte+addressable&pg=PR22|title=Silicon Based Unified Memory Devices and Technology|first=Arup|last=Bhattacharyya|date=6 July 2017|publisher=CRC Press|isbn=9781351798327 |via=Google Books}}</ref><ref>{{Cite book|url=https://books.google.com/books?id=rGjkBQAAQBAJ&dq=nor+random+access+byte+addressable&pg=PA59|title=FUNDAMENTALS OF COMPUTERS|first1=V.|last1=RAJARAMAN|first2=NEEHARIKA|last2=ADABALA|date=15 December 2014|publisher=PHI Learning Pvt. Ltd.|isbn=9788120350670 |via=Google Books}}</ref> while NAND allows only page access.<ref>{{cite web|last=Aravindan|first=Avinash|date=2018-07-23|title=Flash 101: NAND Flash vs NOR Flash|url=https://www.embedded.com/flash-101-nand-flash-vs-nor-flash/|access-date=2020-12-23|website=Embedded.com|language=en-US}}</ref>

NOR<ref>{{cite book | url=https://books.google.com/books?id=7XhhDwAAQBAJ&dq=nor+random+access&pg=PA113 | title=Bits on Chips | isbn=978-3-319-76096-4 | last1=Veendrick | first1=Harry | date=21 June 2018 | publisher=Springer }}</ref> and NAND flash get their names from the structure of the interconnections between memory cells.<ref>{{Cite web |title=NAND and NOR Gates |url=https://bob.cs.sonoma.edu/testing/sec-nand.html |access-date=2024-11-03 |website=bob.cs.sonoma.edu}}</ref> In NOR&nbsp;flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually.<ref name="auto7">{{Cite book|url=https://books.google.com/books?id=vaq11vKwo_kC&dq=nand+flash+xip&pg=PA12|title=Inside NAND Flash Memories|first1=Rino|last1=Micheloni|first2=Luca|last2=Crippa|first3=Alessia|last3=Marelli|date=27 July 2010|publisher=Springer Science & Business Media|isbn=9789048194315 |via=Google Books}}</ref> The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate.<ref>{{Cite book|url=https://books.google.com/books?id=44mbEAAAQBAJ&dq=nor+flash+nor+gate&pg=PA55|title=Springer Handbook of Semiconductor Devices|first1=Massimo|last1=Rudan|first2=Rossella|last2=Brunetti|first3=Susanna|last3=Reggiani|date=10 November 2022|publisher=Springer Nature|isbn=9783030798277 |via=Google Books}}</ref> In NAND&nbsp;flash, cells are connected in series,<ref name="auto7"/> resembling a CMOS NAND gate. The series connections consume less space than parallel ones, reducing the cost of NAND&nbsp;flash.<ref name="auto7"/> It does not, by itself, prevent NAND cells from being read and programmed individually.{{Citation needed|date=September 2020}}