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Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over non-flash EEPROM when writing large amounts of data. {{As of|2019|post=,}} flash memory costs much less than byte-programmable EEPROM and has become the dominant memory type wherever a system required a significant amount of non-volatile [[solid-state storage]]. EEPROMs, however, are still used in applications that require only small amounts of storage, e.g. in [[serial presence detect|SPD]] implementations on computer-memory modules.<ref name="micron-tn-04-42">{{Cite web |title=Memory Module Serial Presence-Detect Introduction |url=https://www.micron.com/-/media/client/global/documents/products/technical-note/dram-modules/tn_04_42.pdf?rev=e5a1537ce3214de5b695f17c340fd023 |url-status=live |archive-url=https://web.archive.org/web/20220726125258/https://www.micron.com/-/media/client/global/documents/products/technical-note/dram-modules/tn_04_42.pdf |archive-date=26 July 2022 |access-date=1 June 2022 |publisher=[[Micron Technology]] |id=TN-04-42 }}</ref><ref name="ti-spd-ref">{{Cite web |date=January 1998 |title=Serial Presence Detect - Technical Reference |url=https://www.ti.com/lit/ug/smmu001/smmu001.pdf |url-status=live |archive-url=https://web.archive.org/web/20231204093906/https://www.ti.com/lit/ug/smmu001/smmu001.pdf |archive-date=4 December 2023 |publisher=[[Texas Instruments]] |id=SMMU001 }}</ref>
Flash memory packages can use [[Three-dimensional integrated circuit|die stacking]] with [[through-silicon via]]s and several dozen layers of 3D TLC NAND cells (per die) simultaneously to achieve capacities of up to 1 [[tebibyte]] per package using 16 stacked dies and an integrated [[flash controller]] as a separate die inside the package.<ref name="anandtech-20190130">{{Cite news |last=Shilov |first=Anton |date=30 January 2019 |title=Samsung Starts Production of 1 TB eUFS 2.1 Storage for Smartphones |work=[[AnandTech]] |url=https://www.anandtech.com/show/13918/samsung-starts-production-of-1-tb-eufs-21-storage-for-smartphones |url-status=
==History==
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[[3D integrated circuit]] (3D IC) technology stacks [[integrated circuit]] (IC) chips vertically into a single 3D IC package.<ref name="James"/> Toshiba introduced 3D IC technology to NAND flash memory in April 2007, when they debuted a 16{{nbsp}}[[Gibibyte|GB]] eMMC compliant (product number THGAM0G7D8DBAI6, often abbreviated THGAM on consumer websites) embedded NAND flash memory package, which was manufactured with eight stacked 2{{nbsp}}GB NAND flash chips.<ref name="toshiba2007"/> In September 2007, [[Hynix Semiconductor]] (now [[SK Hynix]]) introduced 24-layer 3D IC technology, with a 16{{nbsp}}GB flash memory package that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.<ref name="hynix2007"/> Toshiba also used an eight-layer 3D IC for their 32{{nbsp}}GB THGBM flash package and in 2008.<ref name="toshiba2008"/> In 2010, Toshiba used a 16-layer 3D IC for their 128{{nbsp}}GB THGBM2 flash package, which was manufactured with 16 stacked 8{{nbsp}}GB chips.<ref name="toshiba2010"/> In the 2010s, 3D ICs came into widespread commercial use for NAND flash memory in [[mobile devices]].<ref name="James"/>
In 2016, Micron and Intel introduced a technology known as CMOS Under the Array/CMOS Under Array (CUA), Core over Periphery (COP), Periphery Under Cell (PUA), or Xtacking,<ref>{{Cite web|url=https://www.theregister.com/2018/08/06/china_aims_to_build_dramspeed_flash/|title=NAND we'll send foreign tech packing, says China of Xtacking: DRAM-speed... but light on layer-stacking|first=Chris|last=Mellor|website=www.theregister.com}}</ref> in which the control circuitry for the flash memory is placed under or above the flash memory cell array. This has allowed for an increase in the number of planes or sections a flash memory chip has, increasing from two planes to four, without increasing the area dedicated to the control or periphery circuitry. This increases the number of IO operations per flash chip or die, but it also introduces challenges when building capacitors for charge pumps used to write to the flash memory.<ref name="auto8">{{Cite web|url=https://www.anandtech.com/show/16491/flash-memory-at-isscc-2021|archive-url=https://web.archive.org/web/20210219150353/https://www.anandtech.com/show/16491/flash-memory-at-isscc-2021|url-status=dead|archive-date=19 February 2021|title=2021 NAND Flash Updates from ISSCC: The Leaning Towers of TLC and QLC|first=Billy|last=Tallis|website=www.anandtech.com}}</ref><ref>{{Cite news|url=https://www.theregister.com/2018/11/05/sk_hynix_96_layer_flash_chip/|title=What the PUC: SK Hynix next to join big boys in 96-layer 3D NAND land|first=Chris|last=Mellor|website=www.theregister.com}}</ref><ref>{{Cite news|url=https://www.theregister.com/2016/02/22/microns_journey_into_the_depths_of_nonvolatility/|title=Look who's avoided getting chatty about XPoint again. Micron... let's get non-volatile|first=Chris|last=Mellor|website=www.theregister.com}}</ref> Some flash dies have as many as 6 planes.<ref>{{Cite web |last=Alcorn |first=Paul |date=2022-07-26 |title=Micron Takes Lead With 232-Layer NAND Flash, up to 2TB per Chip Package |url=https://www.tomshardware.com/news/micron-takes-lead-with-232-layer-nand-up-to-2tb-per-chip-package |access-date=2024-05-31 |website=Tom's Hardware}}</ref>
As of August 2017, microSD cards with a capacity up to 400 [[gigabyte|GB]] (400 billion bytes) were available.<ref name="sandisk-20170831">{{Cite press release |date=31 August 2017 |title=Western Digital Breaks Boundaries with World's Highest-Capacity microSD Card |url=https://www.sandisk.com/about/media-center/press-releases/2017/western-digital-breaks-boundaries-with-worlds-highest-capacity-microsd-card |url-status=dead |archive-url=https://web.archive.org/web/20170901035345/https://www.sandisk.com/about/media-center/press-releases/2017/western-digital-breaks-boundaries-with-worlds-highest-capacity-microsd-card |archive-date=1 September 2017 |access-date=2 September 2017 |publisher=[[SanDisk]] |place=Berlin }}</ref><ref name="forbes-20170831">{{Cite magazine |last=Bradley |first=Tony |date=31 August 2017 |title=Expand Your Mobile Storage With New 400GB microSD Card From SanDisk |url=https://www.forbes.com/sites/tonybradley/2017/08/31/expand-your-mobile-storage-with-new-400gb-microsd-card-from-sandisk |url-status=live |magazine=[[Forbes]] |archive-url=https://web.archive.org/web/20170901064146/https://www.forbes.com/sites/tonybradley/2017/08/31/expand-your-mobile-storage-with-new-400gb-microsd-card-from-sandisk/ |archive-date=1 September 2017 |access-date=2 September 2017 }}</ref> Samsung combined 3D IC chip stacking with its 3D V-NAND and TLC technologies to manufacture its 512{{nbsp}}GB KLUFG8R1EM flash memory package with eight stacked 64-layer V-NAND chips.<ref name="anandtech-20171205" /> In 2019, Samsung produced a 1024{{nbsp}}[[Gigabyte|GB]] flash package, with eight stacked 96-layer V-NAND package and with QLC technology.<ref name="electronicsweekly-samsung"/><ref name="anandtech-samsung-2018"/>
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In flash memory, each memory cell resembles a standard [[metal–oxide–semiconductor field-effect transistor]] (MOSFET) except that the transistor has two gates instead of one. The cells can be seen as an electrical switch in which current flows between two terminals (source and drain) and is controlled by a floating gate (FG) and a control gate (CG). The CG is similar to the gate in other MOS transistors, but below this is the FG, which is insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, electrons placed on it are trapped. When the FG is charged with electrons, this charge [[electric field screening|screens]] the [[electric field]] from the CG, thus increasing the [[threshold voltage]] (V<sub>T</sub>) of the cell. This means that the V<sub>T</sub> of the cell can be changed between the ''uncharged FG threshold voltage'' (V<sub>T1</sub>) and the higher ''charged FG threshold voltage'' (V<sub>T2</sub>) by changing the FG charge. In order to read a value from the cell, an intermediate voltage (V<sub>I</sub>) between V<sub>T1</sub> and V<sub>T2</sub> is applied to the CG. If the channel conducts at V<sub>I</sub>, the FG must be uncharged (if it were charged, there would not be conduction because V<sub>I</sub> is less than V<sub>T2</sub>). If the channel does not conduct at the V<sub>I</sub>, it indicates that the FG is charged. The binary value of the cell is sensed by determining whether there is current flowing through the transistor when V<sub>I</sub> is asserted on the CG. In a multi-level cell device, which stores more than one [[bit]] per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.
Floating gate MOSFETs are so named because there is an electrically insulating tunnel oxide layer between the floating gate and the silicon, so the gate "floats" above the silicon. The oxide keeps the electrons confined to the floating gate. Degradation or wear (and the limited endurance of floating gate Flash memory) occurs due to the extremely high [[electric field]] (10 million volts per centimeter) experienced by the oxide. Such high voltage densities can break atomic bonds over time in the relatively thin oxide, gradually degrading its electrically insulating properties and allowing electrons to be trapped in and pass through freely (leak) from the floating gate into the oxide, increasing the likelihood of data loss since the electrons (the quantity of which is used to represent different charge levels, each assigned to a different combination of bits in MLC Flash) are normally in the floating gate. This is why data retention goes down and the risk of data loss increases with increasing degradation.<ref name="windbacher-211">{{Cite web |last=Windbacher |first=T. |title=2.1.1 Flash Memory |url=https://www.iue.tuwien.ac.at/phd/windbacher/node14.html |url-status=live |archive-url=https://web.archive.org/web/20231109113308/https://www.iue.tuwien.ac.at/phd/windbacher/node14.html |archive-date=9 November 2023 |website=Engineering Gate Stacks for Field-Effect Transistors }}</ref><ref name="minnesota-floating-gate-mos">{{Cite web |title=Floating Gate MOS Memory |url=http://www.princeton.edu/~chouweb/newproject/research/SEM/FloatMOSMem.html |url-status=dead |archive-url=https://web.archive.org/web/20220808223834/http://www.princeton.edu/~chouweb/newproject/research/SEM/FloatMOSMem.html |archive-date=8 August 2022 |publisher=[[University of Minnesota]] }}</ref><ref name="auto5"/><ref name="anandtech"/><ref name="electronics-notes-wear-levelling">{{Cite web |title=Flash Memory Reliability, Life & Wear |url=https://www.electronics-notes.com/articles/electronic_components/semiconductor-ic-memory/flash-wear-levelling-reliability-lifetime.php |url-status=live |archive-url=https://web.archive.org/web/20231102133652/https://www.electronics-notes.com/articles/electronic_components/semiconductor-ic-memory/flash-wear-levelling-reliability-lifetime.php |archive-date=2 November 2023 |website=Electronics Notes }}</ref> The silicon oxide in a cell degrades with every erase operation. The degradation increases the amount of negative charge in the cell over time due to trapped electrons in the oxide and negates some of the control gate voltage. Over time, this also makes erasing the cell slower; to maintain the performance and reliability of the NAND chip, the cell must be retired from use. Endurance also decreases with the number of bits in a cell. With more bits in a cell, the number of possible states (each represented by a different voltage level) in a cell increases and is more sensitive to the voltages used for programming. Voltages may be adjusted to compensate for degradation of the silicon oxide, and as the number of bits increases, the number of possible states also increases and thus the cell is less tolerant of adjustments to programming voltages, because there is less space between the voltage levels that define each state in a cell.<ref name="auto6">{{Cite news |last=Vättö |first=Kristian |date=23 February 2012 |title=Understanding TLC NAND |work=[[AnandTech]] |url=https://www.anandtech.com/show/5067/understanding-tlc-nand/2 |url-status=
===Fowler–Nordheim tunneling===
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Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a [[BIOS]] ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistors or cells, however the industry can avoid this and achieve higher storage densities per die by using 3D NAND, which stacks cells on top of each other.
NAND flash cells are read by analysing their response to various voltages.<ref name="anandtech">{{Cite news |last=Shimpi |first=Anand Lal |date=30 September 2011 |title=The Intel SSD 710 (200GB) Review |work=[[AnandTech]] |url=https://www.anandtech.com/show/4902/intel-ssd-710-200gb-review |url-status=
====Writing and erasing====
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====Structure====
V-NAND uses a [[charge trap flash]] geometry (which was commercially introduced in 2002 by [[AMD]] and [[Fujitsu]])<ref name="auto3"/> that stores charge on an embedded [[silicon nitride]] film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps a planar charge trap cell into a cylindrical form.<ref name="vnand" /> As of 2020, 3D NAND flash memories by Micron and Intel instead use floating gates, however, Micron 128 layer and above 3D NAND memories use a conventional charge trap structure, due to the dissolution of the partnership between Micron and Intel. Charge trap 3D NAND flash is thinner than floating gate 3D NAND. In floating gate 3D NAND, the memory cells are completely separated from one another, whereas in charge trap 3D NAND, vertical groups of memory cells share the same silicon nitride material.<ref name="anandtech-20201109">{{Cite news |last=Tallis |first=Billy |date=9 November 2020 |title=Micron Announces 176-layer 3D NAND |work=[[AnandTech]] |url=https://www.anandtech.com/show/16230/micron-announces-176layer-3d-nand |url-status=
An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel.<ref name="vnand" />
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| QLC NAND || {{unknown}} || SanDisk X4 NAND flash SD cards<ref>{{cite web|url=https://www.cnet.com/news/sandisk-to-begin-making-x4-flash-chips/|title=SanDisk to begin making 'X4' flash chips|first=Brooke|last=Crothers|website=CNET}}</ref><ref>{{cite web|url=https://www.cnet.com/news/sandisk-ships-x4-flash-chips/|title=SanDisk ships 'X4' flash chips|first=Brooke|last=Crothers|website=CNET}}</ref><ref>{{cite web|url=https://phys.org/news/2009-10-sandisk-ships-memory-cards-gigabit.html|title=SanDisk Ships Flash Memory Cards With 64 Gigabit X4 NAND Technology|website=phys.org}}</ref><ref>{{cite web|url=https://www.photoreview.com.au/news/sandisk-begins-mass-production-of-x4-flash-memory-chips/|title=SanDisk Begins Mass Production of X4 Flash Memory Chips|date=17 February 2012}}</ref>
|-
| 3D SLC NAND || >100,000 || Samsung Z-NAND<ref name="auto2">{{cite web|url=https://www.anandtech.com/show/13951/the-samsung-983-zet-znand-ssd-review|archive-url=https://web.archive.org/web/20190219191320/https://www.anandtech.com/show/13951/the-samsung-983-zet-znand-ssd-review|url-status=dead|archive-date=19 February 2019|title=The Samsung 983 ZET (Z-NAND) SSD Review: How Fast Can Flash Memory Get?|first=Billy|last=Tallis|website=AnandTech.com}}</ref>
|-
| {{nowrap|3D MLC NAND}} || 6,000–40,000 || Samsung SSD 850 PRO, Samsung SSD 845DC PRO,<ref name="AnandTech-SSD850PROEndurance">{{cite web|last1=Vättö|first1=Kristian|title=Testing Samsung 850 Pro Endurance & Measuring V-NAND Die Size|url=http://www.anandtech.com/show/8239/update-on-samsung-850-pro-endurance-vnand-die-size|website=[[AnandTech]]|access-date=11 June 2017|url-status=
|-
| 3D TLC NAND || 1,500–5,000 || Samsung SSD 850 EVO, Samsung SSD 845DC EVO, Crucial MX300<ref name="AnandTech-SamsungSSD850EVOReview-p4">{{cite web|last1=Vättö|first1=Kristian|title=Samsung SSD 850 EVO (120GB, 250GB, 500GB & 1TB) Review|url=http://www.anandtech.com/show/8747/samsung-ssd-850-evo-review/4|website=[[AnandTech]]|access-date=11 June 2017|page=4|url-status=
|-
| 3D QLC NAND || 100–1,500 || Samsung SSD 860 QVO SATA, Intel SSD 660p, Micron 5210 ION, Crucial P1, Samsung SSD BM991 NVMe<ref name="evans-qlc-nand">{{Cite web |last=Evans |first=Chris |date=7 November 2018 |title=QLC NAND - What can we expect from the technology? |url=https://www.architecting.it/blog/qlc-nand/ |url-status=live |archive-url=https://web.archive.org/web/20231102133726/https://www.architecting.it/blog/qlc-nand/ |archive-date=2 November 2023 }}</ref><ref name="micron-20181105">{{Cite press release |last=Dicker |first=Derek |date=5 November 2018 |title=Say Hello: Meet the World's First QLC SSD, the Micron 5210 ION |url=https://www.micron.com/about/blog/2018/november/meet%20the%20worlds%20first%20qlc%20ssd%20the%20micron%205210%20ion |url-status=live |archive-url=https://web.archive.org/web/20190130163245/https://www.micron.com/about/blog/2018/november/meet%20the%20worlds%20first%20qlc%20ssd%20the%20micron%205210%20ion |archive-date=30 January 2019 |publisher=[[Micron Technology]] }}</ref><ref>{{cite web|url=https://www.micron.com/products/advanced%20solutions/qlc%20nand|archive-url=https://web.archive.org/web/20190130091405/https://www.micron.com/products/advanced%20solutions/qlc%20nand|url-status=dead|archive-date=30 January 2019|title=QLC NAND|website=Micron.com}}</ref><ref name="anandtech-20180807">{{Cite news |last=Tallis |first=Billy |title=The Intel SSD 660p SSD Review: QLC NAND Arrives For Consumer SSDs |work=[[AnandTech]] |url=https://www.anandtech.com/show/13078/the-intel-ssd-660p-ssd-review-qlc-nand-arrives |url-status=
|-
| 3D PLC NAND || {{unknown}} || In development by SK Hynix (formerly Intel)<ref name="reuters-20201020">{{Cite news |last1=Jin |first1=Hyunjoo |last2=Nellis |first2=Stephen |last3=Hu |first3=Krystal |last4=Bera |first4=Ayanti |last5=Lee |first5=Joyce |date=20 October 2020 |title=South Korea's SK Hynix to buy Intel's NAND business for $9 billion |editor-last=Coates |editor-first=Stephen |url=https://www.reuters.com/article/us-intel-divestiture-sk-hynix-idUSKBN2742IY |url-status=live |archive-url=https://web.archive.org/web/20231102132619/https://www.reuters.com/article/us-intel-divestiture-sk-hynix-idUSKBN2742IY |archive-date=2 November 2023 |newspaper=[[Reuters]] }}</ref> and [[Kioxia]] (formerly Toshiba Memory).<ref name="auto4" />
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In addition to individual flash memory chips, flash memory is also [[embedded system|embedded]] in [[microcontroller]] (MCU) chips and [[system-on-chip]] (SoC) devices.<ref name="arm">{{Cite conference |last=Yiu |first=Joseph |date=February 2015 |title=Design of SoC for High Reliability Systems with Embedded Processors |url=https://community.arm.com/cfs-file/__key/telligent-evolution-components-attachments/01-2142-00-00-00-00-70-29/Embedded-SoC-Design-for-High-Reliability-Systems-1.02.pdf |conference=Embedded World 2015 |publisher=[[Arm Holdings|ARM]] |archive-url=https://web.archive.org/web/20231204181327/https://community.arm.com/cfs-file/__key/telligent-evolution-components-attachments/01-2142-00-00-00-00-70-29/Embedded-SoC-Design-for-High-Reliability-Systems-1.02.pdf |archive-date=4 December 2023 |access-date=23 October 2019 |url-status=live }}</ref> Flash memory is embedded in [[ARM chips]],<ref name="arm"/> which have sold 150{{nbsp}}billion units worldwide {{as of|2019|lc=y}},<ref name="anandtech-20191008">{{Cite news |last=Smith |first=Ryan |date=8 October 2019 |title=Arm TechCon 2019 Keynote Live Blog (Starts at 10am PT/17:00 UTC) |work=[[AnandTech]] |url=https://www.anandtech.com/show/14959/arm-techcon-2019-keynote-live-blog |url-status=
==Flash scalability==
{{See also|List of semiconductor scale examples|Moore's law}}
Due to its relatively simple structure and high demand for higher capacity, NAND flash memory is the most aggressively [[List of semiconductor scale examples|scaled technology]] among [[electronic devices]]. The heavy competition among the top few manufacturers only adds to the aggressiveness in shrinking the [[floating-gate MOSFET]] design rule or process technology node.<ref name=NEA/> While the expected shrink timeline is a factor of two every three years per the original version of [[Moore's law]], this has recently been accelerated in the case of NAND flash to a factor of two every two years. <!-- In November 2012, Samsung started production of 19 nm NAND chips (marketed them as "10 nm class", explained as something between 10 and 19 nm).<ref>{{cite news |url=http://www.anandtech.com/show/7173/samsung-ssd-840-evo-review-120gb-250gb-500gb-750gb-1tb-models-tested |archive-url=https://archive.today/20150110183324/http://www.anandtech.com/show/7173/samsung-ssd-840-evo-review-120gb-250gb-500gb-750gb-1tb-models-tested |url-status=dead |archive-date=10 January 2015 |title=Samsung SSD 840 EVO Review: 120GB, 250GB, 500GB, 750GB & 1TB Models Tested |last=Anand |first=Lal Shimpi |date=July 25, 2013 |publisher=AnandTech |access-date=9 January 2015}} "''Samsung calls its latest NAND process 10nm-class or 1x-nm, which can refer to feature sizes anywhere from 10nm to 19nm but we've also heard it referred to as 19nm TLC.''"</ref><ref name="objectiveanalysis-firstvnand">{{Cite web |last=Handy |first=Jim |date=July 2014 |title=Samsung samples 3D NAND SSD |url=https://objective-analysis.com/uploads/2014-07-01_Objective_Analysis_Alert_-_Samsung_Samples_3D_NAND_SSD.pdf |url-status=dead |archive-url=https://web.archive.org/web/20150109085810/https://objective-analysis.com/uploads/2014-07-01_Objective_Analysis_Alert_-_Samsung_Samples_3D_NAND_SSD.pdf |archive-date=9 January 2015 |access-date=9 January 2015 |publisher=ObjectiveAnalysis |quote=..Samsung introduced its 19nm NAND by calling it a “10nm-class” product. Once again, the press misunderstood and broadcast to the world that Samsung was ahead of all of its competitors }}</ref><ref name="pcworld-20130725">{{Cite magazine |last=Jacobi |first=Jon L. |last2=Brown |first2=Michael |date=25 July 2013 |title=Samsung's 840 EVO SSD family: Fast, large, and in charge |url=http://www.pcworld.com/article/2045163/samsungs-840-evo-ssd-family-fast-large-and-in-charge.html |url-status=live |magazine=[[PC World]] |archive-url=https://web.archive.org/web/20230329063848/https://www.pcworld.com/article/453057/samsungs-840-evo-ssd-family-fast-large-and-in-charge.html |archive-date=29 March 2023 |access-date=9 January 2015 |quote=the 19nm manufacturing process used to produce the NAND. Samsung for some reason is calling this 10nm-class, or 1x NAND, but they assured us that it's 19nm. }}</ref><ref name="eetimes-20121120">{{Cite news |last=Clarke |first=Peter |date=20 November 2012 |title=Samsung takes NAND memory below 20-nm |work=[[EE Times]] |url=https://www.eetimes.com/Samsung-takes-NAND-memory-below-20-nm/ |url-status=live |access-date=21 December 2012 |archive-url=https://web.archive.org/web/20220206115823/https://www.eetimes.com/samsung-takes-nand-memory-below-20-nm/ |archive-date=6 February 2022 }}</ref> -->
{{clear}}
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As the [[MOSFET]] feature size of flash memory cells reaches the 15–16 nm minimum limit, further flash density increases will be driven by TLC (3 bits/cell) combined with vertical stacking of NAND memory planes. The decrease in endurance and increase in uncorrectable bit error rates that accompany feature size shrinking can be compensated by improved error correction mechanisms.<ref name="anandtech-20101202">{{Cite news |last=Shimpi |first=Anand Lal |date=2 December 2010 |title=Micron's ClearNAND: 25nm + ECC, Combats Increasing Error Rates |work=[[AnandTech]] |url=https://www.anandtech.com/show/4043/micron-announces-clearnand-25nm-with-ecc |url-status=
===Timeline===
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| || KLUFG8R1EM || 4 Tb || Stacked V-NAND || TLC || || Samsung || ? || 150 mm² || <ref name="anandtech-20171205" />
|-
| 2018 || ? || 1 Tb || V-NAND || QLC || || Samsung || ? || ? || <ref name="anandtech-20180806">{{Cite news |last=Shilov |first=Anton |date=6 August 2018 |title=Samsung Starts Mass Production of QLC V-NAND-Based SSDs |work=[[AnandTech]] |url=https://www.anandtech.com/show/13170/samsung-starts-mass-production-of-qlc-vnandbased-ssds |url-status=
|-
| || || 1.33 Tb || V-NAND || QLC || || Toshiba || ? || 158 mm² || <ref name="engadget-20180720">{{Cite news |last=Dent |first=Steve |date=20 July 2018 |title=Toshiba's flash chips could boost SSD capacity by 500 percent |work=[[Engadget]] |url=https://www.engadget.com/2018/07/20/toshiba-flash-166-gb-per-chip/ |url-status=live |access-date=23 June 2019 |archive-url=https://web.archive.org/web/20231106203450/https://www.engadget.com/2018-07-20-toshiba-flash-166-gb-per-chip.html |archive-date=6 November 2023 }}</ref><ref name="eetimes-20190220">{{Cite news |last=McGrath |first=Dylan |date=20 February 2019 |title=Toshiba Claims Highest-Capacity NAND |work=[[EE Times]] |___location=San Francisco |url=https://www.eetimes.com/document.asp?doc_id=1334344 |url-status=live |access-date=23 June 2019 |archive-url=https://web.archive.org/web/20230423012213/https://www.eetimes.com/toshiba-claims-highest-capacity-nand/ |archive-date=23 April 2023 }}</ref>
|-
| 2019 || ? || 512 GB || V-NAND || QLC || || Samsung || ? || ? || <ref name="electronicsweekly-samsung">{{Cite news |last=Manners |first=David |date=30 January 2019 |title=Samsung makes 1TB flash eUFS module |work=[[Electronics Weekly]] |url=https://www.electronicsweekly.com/news/business/samsung-makes-1tb-flash-module-2019-01/ |url-status=live |access-date=23 June 2019 |archive-url=https://web.archive.org/web/20230210114056/https://www.electronicsweekly.com/news/business/samsung-makes-1tb-flash-module-2019-01/ |archive-date=10 February 2023 }}</ref><ref name="anandtech-samsung-2018">{{Cite news |last=Tallis |first=Billy |date=17 October 2018 |title=Samsung Shares SSD Roadmap for QLC NAND And 96-layer 3D NAND |work=[[AnandTech]] |url=https://www.anandtech.com/show/13497/samsung-shares-ssd-roadmap-for-qlc-nand-and-96layer-3d-nand |url-status=
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| || || 1 Tb || V-NAND || TLC || || SK Hynix || ? || ? || <ref name="anandtech-20190626">{{Cite news |last=Shilov |first=Anton |date=26 June 2019 |title=SK Hynix Starts Production of 128-Layer 4D NAND, 176-Layer Being Developed |work=[[AnandTech]] |url=https://www.anandtech.com/show/14589/sk-hynix-128-layer-4d-nand |url-status=
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| || eUFS 2.1 || 1 Tb || Stacked V-NAND<ref name="zdnet-20190129">{{Cite news |last=Mu-Hyun |first=Cho |title=Samsung produces 1TB eUFS memory for smartphones |work=[[ZDNet]] |url=https://www.zdnet.com/article/samsung-produces-1tb-eufs-memory-for-smartphones/ |url-status=live |archive-url=https://web.archive.org/web/20231102133634/https://www.zdnet.com/article/samsung-produces-1tb-eufs-memory-for-smartphones/ |archive-date=2 November 2023 }}</ref> || QLC || 16 of 64 || Samsung || ? || 150 mm² || <ref name="electronicsweekly-samsung" /><ref name="anandtech-samsung-2018" /><ref name="samsung-20190130">{{Cite press release |date=30 January 2019 |title=Samsung Breaks Terabyte Threshold for Smartphone Storage with Industry's First 1TB Embedded Universal Flash Storage |url=https://news.samsung.com/global/samsung-breaks-terabyte-threshold-for-smartphone-storage-with-industrys-first-1tb-embedded-universal-flash-storage |url-status=live |archive-url=https://web.archive.org/web/20231130040907/https://news.samsung.com/global/samsung-breaks-terabyte-threshold-for-smartphone-storage-with-industrys-first-1tb-embedded-universal-flash-storage |archive-date=30 November 2023 |access-date=13 July 2019 |publisher=[[Samsung]] }}</ref>
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