Field-programmable gate array: Difference between revisions

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In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that some FPGAs can be vulnerable to hostile intent. They discovered a critical [[Backdoor (computing)|backdoor vulnerability]] had been manufactured in silicon as part of the Actel/Microsemi ProAsic&nbsp;3 making it vulnerable on many levels such as reprogramming crypto and [[access key]]s, accessing unencrypted bitstream, modifying [[low-level]] silicon features, and extracting [[Computer configuration|configuration]] data.<ref>{{cite book |volume=7428|pages=23–40|doi=10.1007/978-3-642-33027-8_2|series = Lecture Notes in Computer Science|year = 2012|last1 = Skorobogatov|first1 = Sergei|title=Cryptographic Hardware and Embedded Systems – CHES 2012|last2=Woods|first2=Christopher|isbn=978-3-642-33026-1|chapter=Breakthrough Silicon Scanning Discovers Backdoor in Military Chip}}</ref>

In 2020 a critical vulnerability (named Starbleed) was discovered in all Xilinx&nbsp;7 series FPGAs that rendered bitstream encryption useless. There is no workaround. Xilinx did not produce a hardware revision. Ultrascale and later devices, already on the market at the time, were not affected.{{cn|date=July 2025}}<!--[[User:Kvng/RTH]]-->

== Similar technologies ==

Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study from 2006 showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations.<ref name="FPGA-ASIC-comparison">{{cite conference|doi=10.1145/1117201.1117205|chapter=Measuring the gap between FPGAs and ASICs|title=Proceedings of the international symposium on Field programmable gate arrays – FPGA'06|pages=21–30|year=2006|last1=Kuon|first1=Ian|last2=Rose|first2=Jonathan|isbn=1-59593-292-5|publisher=ACM|___location=New York, NY|chapter-url=http://ece.gmu.edu/coursewebpages/ECE/ECE448/S09/viewgraphs/Gap_between_FPGAs_and_ASICs.pdf|conference=|access-date=2017-10-25|archive-date=2010-06-22|archive-url=https://web.archive.org/web/20100622170541/http://ece.gmu.edu/coursewebpages/ECE/ECE448/S09/viewgraphs/Gap_between_FPGAs_and_ASICs.pdf|url-status=dead}}</ref>

Advantages of FPGAs include the ability to re-program whenreprogram alreadyequipment deployed (i.e. "in the field") to fix [[Bug (computer programming)|bugs]], andor oftenmake other improvements. Some FPGAs have the capability of [[partial re-configuration]] that lets one portion of the device be re-programmed while other portions continue running.<ref>{{Cite web|url=https://www.intel.com/content/www/us/en/programmable/documentation/ekx1496870149834.html|title=AN 818: Static Update Partial Reconfiguration Tutorial: for Intel Stratix 10 GX FPGA Development Board|website=www.intel.com|access-date=2018-12-01}}</ref><ref>{{Cite web|url=https://electronics.stackexchange.com/questions/45115/can-fpgas-dynamically-modify-their-logic|title=Can FPGAs dynamically modify their logic?|website=Electrical Engineering Stack Exchange|access-date=2018-12-01}}</ref> Other advantages may include shorter [[time to market]] and lower [[non-recurring engineering]] costs. Vendors can also take a middle road via [[FPGA prototyping]]: developing their prototype hardware on FPGAs, but manufacturemanufacturing their final version as an ASIC so that it can no longer be modified after the design has been committed. This is often also the case with new processor designs.<ref>{{cite web|url=https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|archive-url=https://web.archive.org/web/20190827160514/https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|url-status=dead|archive-date=August 27, 2019|title=Xilinx Announces World Largest FPGA: Virtex Ultrascale+ VU19P with 9m Cells|first=Ian|last=Cutress|date=August 27, 2019|website=[[AnandTech]]}}</ref> Some FPGAs have the capability of [[partial re-configuration]] that lets one portion of the device be re-programmed while other portions continue running.<ref>{{Cite web|url=https://www.intel.com/content/www/us/en/programmable/documentation/ekx1496870149834.html|title=AN 818: Static Update Partial Reconfiguration Tutorial: for Intel Stratix 10 GX FPGA Development Board|website=www.intel.com|access!-date=2018-12-01}}</ref><ref>{{Cite web|url=https[[User:Kvng//electronics.stackexchange.com/questions/45115/canRTH]]-fpgas-dynamically-modify-their-logic|title=Can FPGAs dynamically modify their logic?|website=Electrical Engineering Stack Exchange|access-date=2018-12-01}}</ref>

The primary differences between [[complex programmable logic device]]s (CPLDs) and FPGAs are [[Computer architecture|architectural]]. A CPLD has a comparatively restrictive structure consisting of one or more programmable [[Canonical normal form|sum-of-products]] logic arrays feeding a relatively small number of clocked [[Register (computing)|registers]]. As a result, CPLDs are less flexible but have the advantage of more predictable [[Latency (engineering)|timing delays]] and {{Citation needed span|text=a higher logic-to-interconnect ratio.|date=December 2018|reason=}} FPGA architectures, on the other hand, are dominated by [[Communications subsystem|interconnect]]. This makes them far more flexible (in terms of the range of designs that are practical for implementation on them) but also far more complex to design for, or at least requiring more complex [[electronic design automation]] (EDA) software. In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs. Typically only FPGAs contain more complex [[Functional unit|embedded functions]] such as [[Adder (electronics)|adders]], [[Binary multiplier|multipliers]], [[Computer memory|memory]], and [[SerDes|serializer/deserializers]]. Another common distinction is that CPLDs contain embedded [[flash memory]] to store their configuration while FPGAs usually require external [[non-volatile memory]] (but not always). When a design requires simple instant-on [[glue logic|(logic is already configured at power-up)]] CPLDs are generally preferred. For most other applications FPGAs are generally preferred. Sometimes both CPLDs and FPGAs are used in a single system design. In those designs, CPLDs generally perform glue logic functions and are responsible for "[[booting]]" the FPGA as well as controlling [[Reset (computing)|reset]] and boot sequence of the complete circuit board. Therefore, depending on the application it may be judicious to use both FPGAs and CPLDs in a single design.<ref>{{cite web|url=https://numato.com/kb/cpld-vs-fpga-differences-one-use/|title=CPLD vs FPGA: Differences between them and which one to use? – Numato Lab Help Center|website=numato.com|date=2017-11-29}}</ref>