Instruction set architecture: Difference between revisions

Revision as of 19:12, 27 June 2025

Revision as of 15:41, 10 August 2025

Line 1:

{{Short description |Model that describedescribes software'sthe operationsprogrammable tointerface of a computer processor}}

{{Broader|Computer architecture}}

{{Distinguish|Industry Standard Architecture}}

{{Machine code}}

In [[computer science]], anAn '''instruction set architecture''' ('''ISA''') is an [[abstract model]] that generally defines howthe [[software]]programmable controlsinterface of the [[CPU]] inof a computer; orhow a[[software]] familycan ofcontrol computersa computer.<ref>{{Cite web |title=GLOSSARY: Instruction Set Architecture (ISA) |url=https://www.arm.com/glossary/isa |archive-url=https://web.archive.org/web/20231111175250/https://www.arm.com/glossary/isa |archive-date=2023-11-11 |access-date=2024-02-03 |website=arm.com}}</ref> A device or(i.e. programCPU) that executesinterprets instructions described by thatan ISA, suchis asan a[[implementation]] centralof processingthat unitISA. (CPU)Generally, the same ISA is calledused anfor ''[[implementation]]''a family of thatrelated ISACPU devices.

In general, an ISA defines the supported [[Machine code|instructions]], [[data type]]s, [[Register (computer)|registers]], the hardware support for managing [[Computer memory|main memory]],{{Clarify|date=April 2024|reason=See "What does "Hardware support for managing main memory" refer to?" on the talk page.]]}} fundamental features (such as the [[memory consistency]], [[addressing mode]]s, [[virtual memory]]), and the [[input/output]] model of implementations of the ISA.