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'''Bit manipulation instructions''' are [[instruction set architecture|instructions]] that perform [[bit manipulation]] operations in hardware, rather than requiring several instructions for those operations as illustrated with [[Bit manipulation#Example of bit manipulation|examples in software]].<ref>{{cite web | title=Bit Twiddling Hacks | url=https://graphics.stanford.edu/~seander/bithacks.html}}</ref> Several leading as well as historic architectures have bit manipulation instructions including [[ARM]], [[WDC 65C02]], the [[TX-2]] and the [[Power ISA]].<ref>{{cite web | title=Advanced bit manipulation instructions: Architecture, implementation and applications | website=[[ProQuest]] | url=https://www.proquest.com/openview/0ad3a2474b0691b65b35582fbdb3cf40/1?pq-origsite=gscholar&cbl=18750 }}</ref>
Bit manipulation is usually divided into subsets as individual instructions can be costly to implement in hardware when the target application has no justification. Conversely, if there ''is'' a justification then performance may suffer if the instruction is excluded. Carrying out the cost-benefit analysis is a complex task: one of the most comprehensive efforts in bit manipulation was a collaboration headed by Clare Wolfe, providing justifications, use-cases, c code, proofs and Verilog for each proposed RISC-V instruction.<ref>{{cite web | title=GitHub - riscv/Riscv-bitmanip at v0.93 | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/tree/v0.93 }}</ref><ref>https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmanip-draft.pdf {{Bare URL PDF|date=August 2025}}</ref>
Particular practical examples include [[Bit banging]] of [[GPIO]] using a low-cost [[Embedded controller]] such as the [[WDC 65C02]], [[8051]] and [[PIC instruction listings#Baseline core devices (12-bit)|Atmel PIC]]. At the slow clock rate of these CPUs, if bit-set/clear/test bit manipulation were not available the use of that low-cost CPU would, self-evidently, not be viable for the target application.
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