Random-access memory: Difference between revisions

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{{Redirect|RAM|other uses|RAM (disambiguation)}}

{{Distinguish|Random Access Memories|Random-access machine}}

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===MOS RAM===

In 1957, Frosch and Derick manufactured the first silicon dioxide field-effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref> Subsequently, in 1960, a team demonstrated a working [[MOSFET]] at Bell Labs.<ref>{{Cite journal |last=KAHNG |first=D. |orig-date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories |pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5|url-access=subscription }}</ref><ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |___location=Berlin, Heidelberg |page=321}}</ref> This led to the development of [[metal–oxide–semiconductor]] (MOS) memory by John Schmidt at [[Fairchild Semiconductor]] in 1964.<ref name="computerhistory1970" /><ref>{{Cite book |url=https://books.google.com/books?id=kG4rAQAAIAAJ&q=John+Schmidt |title=Solid State Design – Vol. 6 |date=1965 |publisher=Horizon House}}</ref> In addition to higher speeds, MOS [[semiconductor memory]] was cheaper and consumed less power than magnetic core memory.<ref name="computerhistory1970" /> The development of [[silicon-gate]] [[MOS integrated circuit]] (MOS IC) technology by [[Federico Faggin]] at Fairchild in 1968 enabled the production of MOS [[memory chip]]s.<ref>{{cite web |title=1968: Silicon Gate Technology Developed for ICs |url=https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |website=[[Computer History Museum]] |access-date=10 August 2019}}</ref> MOS memory overtook magnetic core memory as the dominant memory technology in the early 1970s.<ref name="computerhistory1970" />

Integrated bipolar [[static random-access memory]] (SRAM) was invented by Robert H. Norman at [[Fairchild Semiconductor]] in 1963.<ref>{{cite patent

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[[Dynamic random-access memory]] (DRAM) allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor and had to be periodically [[Memory refresh|refreshed]] every few milliseconds before the charge could leak away.

[[Toshiba]]'s Toscal BC-1411 [[electronic calculator]], which was introduced in 1965,<ref>[http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator Toscal BC-1411 calculator]. {{webarchive|url=https://web.archive.org/web/20170729145228/http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator |date=2017-07-29 }}, [[Science Museum, London]].</ref><ref name="bc-spec" /><ref name="bc" /> used a form of capacitor bipolar DRAM, storing 180-bit data on discrete [[Memory cell (computing)|memory cells]], consisting of [[germanium]] bipolar transistors and capacitors.<ref name="bc-spec" /><ref name="bc" /> Capacitors had also been used for earlier memory schemes, such as the drum of the [[Atanasoff–Berry Computer]], the [[Williams tube]] and the [[Selectron tube]]. While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum}}</ref>

[[File:Bundesarchiv Bild 183-1989-0406-022, VEB Carl Zeiss Jena, 1-Megabit-Chip.jpg|thumb|right|CMOS 1-[[megabit]] (Mbit) DRAM chip, one of the last models developed by [[VEB Carl Zeiss Jena]], in 1989]]

In 1966, [[Robert Dennard]], while examining the characteristics of MOS technology, found it was capable of building [[capacitor]]s, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, and the MOS transistor could control writing the charge to the capacitor. This led to his development of modern DRAM architecture for which there is a single MOS transistor per capacitor.<ref name="ibm100"/> In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology.<ref name="ibm100" /><ref name="Robert Dennard"/> The first commercial DRAM IC chip was the [[Intel 1103]], which was [[Semiconductor manufacturing process|manufactured]] on an [[10 μm process|8{{nbsp}}μm]] MOS process with a capacity of 1{{nbsp}}[[Kilobit|kbit]], and was released in 1970.<ref name="computerhistory1970"/><ref name="Lojek-1103"/><ref>{{cite web |first=Mary |last=Bellis |url=http://inventors.about.com/library/weekly/aa100898.htm |title=Who Invented the Intel 1103 DRAM Chip? |access-date=2025-03-03 |archive-date=2020-03-14 |archive-url=https://web.archive.org/web/20200314061801/http://inventors.about.com/library/weekly/aa100898.htm |url-status=dead }}</ref>

The earliest DRAMs were often synchronized with the CPU clock and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book |author=P. Darche |url=https://books.google.com/books?id=rLC9zQEACAAJ |title=Microprocessor: Prolegomenes - Calculation and Storage Functions - Calculation Models and Computer |year=2020 |isbn=9781786305633 |page=59| publisher=John Wiley & Sons }}</ref><ref>{{cite book |author1=B. Jacob |url=https://books.google.com/books?id=SrP3aWed-esC |title=Memory Systems: Cache, DRAM, Disk |author2=S. W. Ng |author3=D. T. Wang |publisher=Morgan Kaufmann |year=2008 |isbn=9780080553849 |page=324}}</ref> In 1992 Samsung released KM48SL2000, which had a capacity of 16{{nbsp}}[[Mbit]].<ref name="electronic-design">{{cite journal |title=Electronic Design |journal=[[Electronic Design]] |date=1993 |volume=41 |issue=15–21 |url=https://books.google.com/books?id=QmpJAQAAIAAJ |publisher=Hayden Publishing Company |quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref><ref>{{cite web |title=KM48SL2000-7 Datasheet |url=https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |publisher=[[Samsung]] |access-date=19 June 2019 |date=August 1992}}</ref> The first commercial [[double data rate]] SDRAM was Samsung's 64{{nbsp}}Mbit [[DDR SDRAM]], released in June 1998.<ref>{{cite news |title=Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=10 February 1999}}</ref> [[GDDR]] (graphics DDR) is a form of [[SGRAM]] (synchronous graphics RAM), which was first released by Samsung as a 16{{nbsp}}Mbit memory chip in 1998.<ref>{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=17 September 1998}}</ref>

==Types==

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Usually several memory cells share the same address. For example, a 4 bit "wide" RAM chip has four memory cells for each address. Often the width of the memory and that of the microprocessor are different, for a 32 bit microprocessor, eight 4 bit RAM chips would be needed.

Often more addresses are needed than can be provided by a device. In that case, external multiplexors to the device are used to activate the correct device that is being accessed. RAM is often byte addressable, although it is also possible to make RAM that is word-addressable.<ref>{{cite book | url=https://books.google.com/books?id=QGPHAl9GE-IC&dq=size+of+a+memory+address&pg=PA321 | isbn=978-0-7637-3769-6 | title=The Essentials of Computer Organization and Architecture | date=2006 | publisher=Jones & Bartlett Learning }}</ref><ref>{{cite book | url=https://books.google.com/books?id=-vQCEAAAQBAJ | title=Foundations of Computer Technology | isbn=978-1-000-15371-2 | last1=Anderson | first1=Alexander John | date=25 October 2020 | publisher=CRC Press }}</ref>

==Memory hierarchy==

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==Memory wall==

The '''memory wall''' is the growing disparity of speed between CPU and the response time of memory (known as [[memory latency]]) outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries, which is also referred to as ''bandwidth wall''. From 1986 to 2000, [[CPU]] speed improved at an annual rate of 55% while off-chip memory response time only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming [[bottleneck (engineering)|bottleneck]] in computer performance.<ref>The term was coined in {{cite web |url=http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf |title=Archived copy |access-date=2011-12-14 |url-status=live |archive-url=https://web.archive.org/web/20120406111104/http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf |archive-date=2012-04-06 }}.</ref>

Another reason for the disparity is the enormous increase in the size of memory since the start of the PC revolution in the 1980s. Originally, PCs contained less than 1 mebibyte of RAM, which often had a response time of 1 CPU clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes longer for signals to traverse a larger circuit. Constructing a memory unit of many gibibytes with a response time of one clock cycle is difficult or impossible. Today's CPUs often still have a mebibyte of 0 wait state cache memory, but it resides on the same chip as the CPU cores due to the bandwidth limitations of chip-to-chip communication. It must also be constructed from static RAM, which is far more expensive than the dynamic RAM used for larger memories. Static RAM also consumes far more power.