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===DRAM===
Like NAND Flash, DRAM has also made regular use of multiple patterning. Even though the active areas form a two-dimensional array, one cut mask is sufficient for 20 nm.<ref>Y-S. Kang et al., J. Micro/Nanolith. MEMS MOEMS vol. 15(2), 021403 (2016).</ref> Furthermore, the cut mask may be simultaneously used for patterning the periphery, and thus would not count as an extra mask.<ref>U.S. Patent 7253118.</ref> When the active area long pitch is ~3.5 x the short pitch, the breaks in the active area form a hexagonal array, which is amenable to the triangular lattice spacer patterning mentioned above. Samsung has already started manufacturing the 18 nm DRAM.<ref>[http://www.techinsights.com/about-techinsights/overview/blog/samsung-18-nm-dram-cell-integration-qpt-and-higher-uniformed-capacitor-high-k-dielectrics/ Samsung 18 nm DRAM]</ref> Multiple exposures may be used for the periphery metal routing of DRAM, but this is also unnecessary, as a triple spacer approach offers 1/5 pitch reduction.<ref>[https://www.youtube.com/watch?v=gbwQ0dqyYU8 Triple Spacer Patterning for DRAM Periphery Metal]</ref>
Crossed self-aligned quadruple patterning is used for patterning the capacitor arrays in state-of-the-art DRAM, as of 2025.<ref>[https://chentfred.substack.com/p/crossed-self-aligned-multipatterning Crossed Self-Aligned Multipatterning For Sub-40 nm Pitch Grids: A Process On Record For DRAM]</ref><ref>Md. S. Rahman et al., Proc. SPIE 13427, 134270G (2025).</ref>
===NAND flash===
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