Flash memory: Difference between revisions

Revision as of 05:35, 6 August 2025

Revision as of 13:13, 17 August 2025

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[[File:NOR flash layout.svg|thumb|350px|right| NOR flash memory wiring and structure on silicon]]

In both NOR and NAND flash memories, the cells are arranged in a grid. We can think of the memory as consisting of "words" of a certain number of bits (or cells), with each word being confined to a particular column of the grid, and the bits being in different rows. All the bits of a particular word are linked by a [[wikt:wordline|wordline]], a conductor connecting to the control gates of all the bits of that word. All the first bits of a certain number of adjacent words (columns) are linked by a [[wikt:bitline|bitline]], as are all the second bits and so on. The bitlines connect to one of the terminals (source or drain) of the cells. By manipulating the voltages on the wordlines one can read a certain bit by measuring the voltage on the corresponding bitline. The way to do this depends on whether the memory chip is a NOR or a NAND flash.

In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a [[NOR gate|NOR&nbsp;gate]]; when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device.{{citation needed|date=May 2022}} The low read latencies characteristic of NOR&nbsp;devices allow for both direct code execution and data storage in a single memory product.<ref name="eetimes-20110502">{{Cite news |last=Zitlaw |first=Cliff |date=2 May 2011 |title=The Future of NOR Flash Memory |work=Memory Designline |publisher=UBM Media |url=https://www.eetimes.com/the-future-of-nor-flash-memory/ |url-status=live |access-date=3 May 2011 |archive-url=https://web.archive.org/web/20230601001439/https://www.eetimes.com/the-future-of-nor-flash-memory/ |archive-date=1 June 2023 }}</ref>

In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a [[NOR gate|NOR&nbsp;gate]] {{dash}} if any of the word lines (connected to the CG of the cells) is brought high, the corresponding storage transistor may act to pull the output bit line low, but this depends on the charge in the floating gate. Since several words are connected by the bit line, the output does not depend on only two (the bitline staying high if neither the first NOR the second wordline is high) but on all (the bitline remaining high if NONE of the wordlines is high). So to read a bit of a certain word, all the wordlines except that of the desired word are put low.

In NOR flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a [[NOR gate|NOR&nbsp;gate]]; when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device.{{citation needed|date=May 2022}} The low read latencies characteristic of NOR&nbsp;devices allow for both direct code execution and data storage in a single memory product.<ref name="eetimes-20110502">{{Cite news |last=Zitlaw |first=Cliff |date=2 May 2011 |title=The Future of NOR Flash Memory |work=Memory Designline |publisher=UBM Media |url=https://www.eetimes.com/the-future-of-nor-flash-memory/ |url-status=live |access-date=3 May 2011 |archive-url=https://web.archive.org/web/20230601001439/https://www.eetimes.com/the-future-of-nor-flash-memory/ |archive-date=1 June 2023 }}</ref>

====Programming====

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===NAND flash===

NAND flash also uses a grid of [[Floating-gate MOSFET|floating-gate transistor]]s (see above), but they are connected in a way that resembles a [[NAND&nbsp;gate]]: severalthe transistors corresponding to a given bit of several words are connected in series, and the bit linebitline is pulled low only if all the word lines are pulled high (above the transistors' V_T). To read the bit of a particular word, its wordline is put low and all the other wordlines are put high, and then the bitline will reflect the state of the floating gate of the desired cell. These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR&nbsp;flash.

Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR&nbsp;flash might address memory by page then word, NAND&nbsp;flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only one bit at a time. {{nowrap|Execute-in-place}} applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND&nbsp;flash.