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Under urging by executives such as Jim Hogan and executive vice president [[Penny Herscher]], between 2001 and 2003, Cadence purchased a number of implementation tools through acquisition, such as Silicon Perspective, Verplex,<ref name="Ref_staff13_EETImes.com"/> and [[Chenming Hu|Celestry Design]].<ref name="OriginalRef_staff4_edn.com"/> The acquisitions were apparently in part to counter the 2001 purchase of [[Synopsys#Avanti Corporation|Avanti]] by [[Synopsys]], as Synopsys had become their primary market rival.<ref name="Ref_staff13_EETImes.com"/> In 2004, Mike Fister became Cadence's new CEO and president, with Ray Bingham becoming chairman. The former chairman, Donald L. Lucas, remained on the Cadence board.<ref>WSJ [https://www.wsj.com/articles/SB108439313804409685 Intel's Michael Fister Resigns To Take Top Job at Cadence] Retrieved May 13, 2004</ref> Between 2004 and 2007, Cadence purchased four companies, including the software developer [[Rob A. Rutenbar|Verisity]], and in 2006, it spent $1 billion in [[stock buyback]]s.<ref name="OriginalRef_Sorkin_nytim.com"/>
In 2007, Cadence announced it would be introducing a new chip-making process that laid wires diagonally as well as horizontally and vertically
===2020–2025===
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===Hardware emulation===
In 2015, Cadence announced the '''Palladium''' Z1 [[hardware emulation]] platform,<ref>EE Journal [https://www.eejournal.com/article/20160606-emulation/ State of Emulation] Retrieved June 6, 2016</ref>
The '''Protium''' [[FPGA prototyping]] platform was introduced in 2014,<ref>EDN [https://www.edn.com/cadence-unveils-protium-fpga-based-soc-prototyping-platform/ Cadence unveils Protium FPGA-based SoC prototyping platform] Retrieved July 14, 2014</ref> followed by the Protium S1 in 2017, which was built on [[Xilinx]] Virtex UltraScale [[FPGAs]].<ref>EET Asia [https://www.eetasia.com/multi-core-parallel-engine-powers-cadence-simulator/ Multi-core parallel engine powers Cadence simulator] Retrieved March 1, 2017</ref> Protium X1 rack-based prototyping was introduced in 2019,<ref>Tech Design Forum [https://www.techdesignforums.com/blog/2019/05/28/cadence-expands-protium-for-rack-based-prototyping/ Cadence Expands Protium for Rack-Based Prototyping] Retrieved May 28, 2019</ref> which Cadence claimed supported a 1.2 billion gate SoCs at around 5 MHz.<ref>Electronics Weekly [https://www.electronicsweekly.com/news/design/eda-and-ip/cadence-machine-can-prototype-1bn-gate-soc-fpgas-2019-05/ Cadence machine can prototype a 1bn gate SoC on FPGAs] Retrieved May 29, 2019</ref> with Palladium S1/X1 and Protium sharing a single compilation flow.<ref>EE Journal [https://www.eejournal.com/article/cadence-eda-update/ Cadence EDA Update] Retrieved May 8, 2017</ref> In 2021, Protium X2 was announced; Cadence claimed a 1.5X performance and 2X capacity improvement over Protium X1.<ref>Embedded [https://www.embedded.com/cadence-speeds-billion-gate-soc-verification/ Cadence speeds billion gate SoC verification] Retrieved Apr 7, 2021</ref><ref>New Electronics [https://www.newelectronics.co.uk/electronics-news/cadence-unveils-next-generation-palladium-z2-and-protium-x2-systems/236026/ Cadence unveils next-generation Palladium Z2 and Protium X2 systems] Retrieved Apr 6, 2021</ref>
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