Cadence Design Systems: Difference between revisions

Revision as of 23:36, 24 August 2025

Revision as of 23:38, 24 August 2025

Line 67:

===Hardware emulation===

In 2015, Cadence announced the '''Palladium''' Z1 [[hardware emulation]] platform,<ref>EE Journal [https://www.eejournal.com/article/20160606-emulation/ State of Emulation] Retrieved June 6, 2016</ref> for verifying billion-gate designs.<ref>Electronic Specifier [https://www.electronicspecifier.com/products/design-automation/enterprise-emulation-platform-develops-supercomputer Enterprise Emulation Platform Develops Supercomputer] Retrieved October 26, 2016</ref> which was based on emulation technology from Cadence's 1998 acquisition of Quickturn.<ref name="OriginalRef_Staff3_nytimes.com">NY Times [https://www.nytimes.com/1998/12/10/business/cadence-to-acquire-quickturn-design.html Cadence to Acquire Quickturn Design] Retrieved 36137</ref> Cadence announced Palladium Z2 in 2021, claimingas a 1.5Xsuccessor performanceto andthe 2XZ1 capacityplatform improvementwith overimproved the Z1performance.<ref>Neowin [https://www.neowin.net/news/cadences-latest-palladium-and-protium-dynamic-duo-to-offer-2x-capacity-and-15x-gains/ Cadence's latest Palladium and Protium "dynamic duo" to offer 2X capacity and 1.5X gains] Retrieved Apr 5, 2021</ref><ref>EENews Europe [https://www.eenewseurope.com/news/cadence-boosts-its-emulation-and-verification-systems Cadence boosts its emulation and verification systems] Retrieved Apr 5, 2021</ref>

The '''Protium''' [[FPGA prototyping]] platform was introduced in 2014,<ref>EDN [https://www.edn.com/cadence-unveils-protium-fpga-based-soc-prototyping-platform/ Cadence unveils Protium FPGA-based SoC prototyping platform] Retrieved July 14, 2014</ref> followed by the Protium S1 in 2017, which was built on [[Xilinx]] Virtex UltraScale [[FPGAs]].<ref>EET Asia [https://www.eetasia.com/multi-core-parallel-engine-powers-cadence-simulator/ Multi-core parallel engine powers Cadence simulator] Retrieved March 1, 2017</ref> Protium X1 rack-based prototyping was introduced in 2019,<ref>Tech Design Forum [https://www.techdesignforums.com/blog/2019/05/28/cadence-expands-protium-for-rack-based-prototyping/ Cadence Expands Protium for Rack-Based Prototyping] Retrieved May 28, 2019</ref> which Cadence claimed supported a 1.2 billion gate SoCs at around 5&nbsp;MHz.<ref>Electronics Weekly [https://www.electronicsweekly.com/news/design/eda-and-ip/cadence-machine-can-prototype-1bn-gate-soc-fpgas-2019-05/ Cadence machine can prototype a 1bn gate SoC on FPGAs] Retrieved May 29, 2019</ref> with Palladium S1/X1 and Protium sharing a single compilation flow.<ref>EE Journal [https://www.eejournal.com/article/cadence-eda-update/ Cadence EDA Update] Retrieved May 8, 2017</ref> In 2021, Protium X2 was announced; Cadence claimed a 1.5X performance and 2X capacity improvement over Protium X1.<ref>Embedded [https://www.embedded.com/cadence-speeds-billion-gate-soc-verification/ Cadence speeds billion gate SoC verification] Retrieved Apr 7, 2021</ref><ref>New Electronics [https://www.newelectronics.co.uk/electronics-news/cadence-unveils-next-generation-palladium-z2-and-protium-x2-systems/236026/ Cadence unveils next-generation Palladium Z2 and Protium X2 systems] Retrieved Apr 6, 2021</ref>