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The aperiodic interrupts offered by the APIC timer are used by the [[Linux kernel]] [[tickless kernel]]
feature. This optional but default feature is new with 2.6.18. When enabled on a computer with an APIC timer, the kernel does not use the [[8253]] [[programmable interval timer]] for timekeeping.<ref>{{cite web|url=http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|title=VMware Knowledge Base|website=kb.vmware.com|access-date=2014-02-13|archive-date=2017-02-27|archive-url=https://web.archive.org/web/20170227025032/http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|url-status=dead}}</ref> A [[VMware]] document notes that "software does not have a reliable way to determine its frequency. Generally, the only way to determine the local APIC timer’s frequency is to measure it using the PIT or CMOS timer, which yields only an approximate result."<ref name="vmware">[http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf Timekeeping in VMware Virtual Machines (for VMware vSphere 5.0, Workstation 8.0, Fusion 4.0)] {{Webarchive|url=https://web.archive.org/web/20160626142735/http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf |date=2016-06-26 }}, page 8</ref>
==I/O APICs==
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== Competition ==
{{further|OpenPIC and IBM MPIC}}
[[AMD]] and [[Cyrix]] once proposed a somewhat similar-in-purpose [[OpenPIC]] architecture supporting up to 32 processors;<ref>{{cite web |url=https://www.pcmag.com/encyclopedia_term/0,2542,t=OpenPIC&i=48497,00.asp |title=OpenPIC Definition from PC Magazine Encyclopedia |publisher=Pcmag.com |date=1994-12-01 |access-date=2011-11-03 }}{{Dead link|date=August 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> it had at least declarative support from [[IBM]] and [[Compaq]] around 1995.<ref name="Inc.1995">{{cite journal|title=AMD, Cyrix offer up alternative SMP spec|author=Brooke Crothers|journal=[[InfoWorld]]|url=https://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8|date=20 March 1995|page=8|issn=0199-6649}}</ref> No x86 motherboard was released with OpenPIC however.<ref>André D. Balsa, [http://linuxgazette.net/issue24/Article3e-7.html Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results"] appearing in Issue 24 of Linux Gazette, January 1998</ref> After the OpenPIC's failure in the x86 market, AMD licensed Intel's APIC for its [[AMD Athlon]] and later processors.
IBM however developed their [[OpenPIC and MPIC|MultiProcessor Interrupt Controller]] (MPIC) based on the OpenPIC register specifications.<ref>IBM [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf Multiprocessor Interrupt Controller. Data Book] {{webarchive|url=https://web.archive.org/web/20140223012746/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/%24file/mpic_db_05_16_2011.pdf |date=2014-02-23 }}</ref> MPIC was used in [[PowerPC]] based designs, including those of IBM, for instance in some [[RS/6000]] systems,<ref>Arca Systems TTAP Evaluation Facility [http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security], p. 29</ref> but also by Apple, as late as their [[Power Mac G5]]s.<ref>{{cite book|url=http://www.informit.com/articles/article.aspx?p=606582|title=Take a Look Inside the G5-Based Dual-Processor Power Mac|first=Amit|last=Singh|date=13 October 2006|via=informIT database}}</ref><ref>[https://developer.apple.com/legacy/library/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/PowerMacG5.pdf Power Mac G5 Developer Note (Legacy)], p. 26</ref>
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