Transaction-level modeling: Difference between revisions

Revision as of 14:40, 12 July 2025

Latest revision as of 11:00, 29 August 2025

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{{Short description|Approach for digital systems design}}

'''Transaction-level modeling''' ('''TLM''') is an approach to modelling complex digital systems by using [[electronic design automation]] software.<ref name="TVLSIHB-2007">{{Cite book |title=The VLSI handbook |date=2007 |publisher=CRC/Taylor & Francis |others=Wai-Kai Chen |isbn=978-0-8493-4199-1 |edition=2 |___location=Boca Raton, FL |oclc=70699056}}</ref>{{Rp|page=1955}} TLM is used primarily in the design and verification of complex [[System-on-a-chip|systems-on-chip]] (SoCs) and other electronic systems where traditional [[register-transfer level]] (RTL) modeling would be too slow or resource-intensive for system-level analysis. TLM language (TLML) is a [[hardware description language]], usually, written in C++ and based on [[SystemC]] library.<ref name="TVLSIHB-2007" /> TLMLs are used for modelling where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. It's used for modelling of systems that involve complex data communication mechanisms.{{r|TVLSIHB-2007|pp=1955}} The modeling approach focuses on the ''transactions'' or ''transfers'' of data between functional blocks rather than the detailed implementation of those blocks or their interconnections.<ref name="IEEE_TLM_Standard">{{cite journal |title=IEEE Standard for Standard SystemC Language Reference Manual |journal=IEEE STD 1666-2011 |year=2012 |url=https://ieeexplore.ieee.org/document/6134619 |doi=10.1109/IEEESTD.2012.6134619|isbn=978-0-7381-6801-2 }}</ref> This abstraction enables faster simulation speeds, often orders of magnitude faster than RTL, while maintaining sufficient accuracy for system-level design decisions, [[software development]], and architectural exploration.<ref name="Ghenassia_TLM">{{cite book |title=Transaction-Level Modeling with SystemC |editor=Ghenassia, Frank |publisher=Springer |year=2005 |isbn=978-0-387-26233-4}}</ref>

Components such as buses or [[FIFO (computing and electronics)|FIFOs]] are modeled as channels, and are presented to modules using [[SystemC]] interface classes. Transaction requests take place by calling interface functions of these channel models, which encapsulate low-level details of the information exchange. At the transaction level, the emphasis is more on the functionality of the data transfers – what data are transferred to and from what locations – and less on their actual implementation, that is, on the actual protocol used for data transfer. This approach makes it easier for the system-level designer to experiment, for example, with different bus architectures (all supporting a common abstract interface) without having to recode models that interact with any of the buses, provided these models interact with the bus through the common interface.<ref>T. Grötker, S. Liao, G. Martin, S. Swan, System Design with SystemC. Springer, 2002, Chapter 8., pp. 131. {{ISBN|1-4020-7072-1}} (quoted with permission)</ref>

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TLM is typically implemented using [[SystemC]], a [[C++]]-based modeling language and library developed specifically for system-level design.<ref name="SystemC_Standard">{{cite web |url=https://www.accellera.org/downloads/standards/systemc |title=SystemC Standards |publisher=Accellera Systems Initiative |access-date=2024-01-15}}</ref> The [[Open SystemC Initiative]] (OSCI), now part of [[Accellera]], has developed standardized TLM libraries that provide common interfaces and methodologies for transaction-level communication. However, the application of transaction-level modeling is not specific to the SystemC language and can be used with other languages. The concept of TLM first appears in the system-level language and modeling ___domain.<ref>L. Cai, D. Gajski, Transaction Level Modeling: An Overview, in proceedings of the Int. Conference on HW/SW Codesign and System Synthesis (CODES-ISSS), Oct. 2003, pp. 19–24</ref>

The methodology has become essential in modern [[electronic design automation]] (EDA) flows, particularly for creating [[virtual platform]]s that enable early [[software development]] and system validation before hardware implementation is complete.<ref name="Virtual_Platforms">{{cite conference |title=Virtual Platforms in System-Level Design |author=Schirner, Gunar |conference=Design Automation Conference |year=2013 |pages=804–809 |doi=10.1145/2463209.2488885|doi-broken-date=1 July 2025 }}</ref> TLM models serve as executable specifications that bridge the gap between high-level system requirements and detailed hardware implementations. TLMs are used for [[high-level synthesis]] of [[register-transfer level]] (RTL) models for a lower-level modelling and implementation of system components. RTL is usually represented by a [[hardware description language]] source code (e.g. [[VHDL]], [[SystemC]], [[Verilog]]).{{r|TVLSIHB-2007|pp=1955-1957}}

==Background and history==

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* Enhanced debugging and analysis capabilities<ref name="Aynsley_TLM2">{{cite book |title=ASIC and FPGA Verification: A Guide to Component Modeling |author=Aynsley, John |publisher=Springer |year=2009 |chapter=TLM-2.0 Reference |pages=145–198 |isbn=978-1-4419-0564-5}}</ref>

TLM-2.0 was subsequently incorporated into the [[IEEE]] 1666-2011 standard for SystemC, providing official recognition and broader industry acceptance.<ref name="IEEE_1666_2011IEEE_TLM_Standard">{{cite tech report |title=IEEE Standard for Standard SystemC Language Reference Manual |standard=IEEE Std 1666-2011 |publisher=IEEE |year=2012 |doi=10.1109/IEEESTD.2012.6134619}}</ref>

===Industry adoption and commercial tools===

By the mid-2000s, major [[Electronicelectronic Designdesign Automation|EDAautomation]] companies began incorporating TLM support into their commercial tools. [[Mentor Graphics]] (now [[Siemens EDA]]) introduced TLM support in their ModelSim simulator in 2004,<ref name="ModelSim_TLM">{{cite news |title=Mentor Graphics Adds SystemC TLM to ModelSim |newspaper=EE Times |date=2004-03-15}}</ref> followed by [[Cadence Design Systems]] with their Incisive platform in 2005.<ref name="Cadence_TLM">{{cite press release |title=Cadence Introduces Transaction-Level Modeling Flow |publisher=Cadence Design Systems |date=2005-09-12}}</ref>

Virtual platform companies such as [[CoWare]] (acquired by Synopsys in 2010),<ref name="Synopsys_CoWare">{{cite news |title=Synopsys Acquires CoWare for Virtual Prototyping |newspaper=EE Times |date=2010-02-22}}</ref> Vast Systems (acquired by Synopsys in 2007), and VaST Systems Technology contributed significantly to TLM's commercial adoption by providing high-performance virtual platforms based on TLM methodology.<ref name="Virtual_Platform_Market">{{cite report |title=Virtual Prototyping Market Analysis |publisher=Gary Smith EDA |year=2010}}</ref>