Bit manipulation instructions: Difference between revisions

Revision as of 22:16, 25 August 2025

Revision as of 20:50, 30 August 2025

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=== RISC-V ===

In the standard extensions RISC-V has scalar [[bitwise operations]] including shift and arithmetic shift, but no rotate. The omissions are compensated for with additional extensions.

* [[RISC-V]] Zb* extensions contain a significant number of bit manipulation instructions.<ref>{{cite web | title=Riscv-bitmanip/Bitmanip/Index.adoc at main · riscv/Riscv-bitmanip | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/index.adoc }}</ref> The four groups are broken down into useful categories (the integer subset has min/max, rotate and [[Popcount]] for example), and have very good well-researched justifications for their inclusion and the improvements they bring.<ref>{{cite web | title=Riscv-bitmanip/Bitmanip/Overview.adoc at main · riscv/Riscv-bitmanip | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/overview.adoc }}</ref>

* The RISC-V Vector Extension (RVV) has instructions that qualify as hardware-level bit manipulation, but on Vector masks rather than Scalar registers as is normally the case. For example, a Vector-mask [[Popcount]] is available.<ref>{{cite web | title=Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec | website=[[GitHub]] | url=https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#15-vector-mask-instructions }}</ref> RVV also has per-element [[bitwise operations]].<ref>{{cite web | title=Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec | website=[[GitHub]] | url=https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#115-vector-bitwise-logical-instructions }}</ref>