Manycore processing unit: Difference between revisions

Revision as of 00:34, 28 June 2007

Revision as of 23:04, 28 June 2007

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* many standard [[instruction set]] [[microprocessor]] [[Multi-core (computing)|cores]],

* integrated low-[[Latency (engineering)|latency]] [[memory controller]],

* hardware [[accelerator (computing)|acceleration]] features for [[packet]] handling. Manycore processors make better use of silicon real estate and have lower power requirements that monolithic sequential processors.

Current software architectures can scale on current [[Multi-core (computing)|multicore]] architectures to about eight processors but have poor ability to scale beyond that number.

MPUs have emerged since 2000 as a new class of processor used for [[Embedded system|embedded]] applications in [[telecommunications]], [[computer network|networking]] and other applications.

With the introduction of multiple cores per processor '''manycore''' devices are generally considered to be processors with greater than eight cores.

Somewhat confusingly, if the processor is used for general-purpose computing,

Beyond eight cores a new programming paradigm must be found for general purpose computing that provides support for parallel programing in applications.

rather than embedded or special-purpose applications, it is termed

''[[Multi-core (computing)|multi-core]]'' rather than ''many-core.''

== History and evolution ==

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* [[Data compression|Compression]] and decompression, necessary for inspection of compressed data

* Fast interfaces to external search devices such as [[Content-addressable memory|ternary content-addressable memories]], deep packet [[parsers]], [[longest prefix match]] engines etc.

== Manycore Programming Models ==

As of 2007 no viable programming models for manycore architectures existed.

== MPU applications ==