Design for testing: Difference between revisions

Revision as of 11:52, 23 May 2007

Revision as of 22:36, 10 July 2007

Line 10:

Over the years the industry has developed and used a large variety of more or less detailed and more or less formal guidelines for desired and/or mandatory DFT circuit modifications. The common understanding of DFT in the context of [[Electronic design automation|Electronic Design Automation]] (EDA) for modern microelectronics is shaped to a large extent by the capabilities of commercial DFT software tools as well as by the expertise and experience of a professional community of DFT engineers researching, developing, and using such tools. Much of the related body of DFT knowledge focuses on digital circuits while DFT for analog/mixed-signal circuits takes somewhat of a backseat.

== Objectives of DFT for Microelectronicsmicroelectronics Productsproducts ==

DFT affects and depends on the methods used for test development, test application, and diagnostics.

Line 19:

One benefit of the Structural paradigm is that test generation can focus on testing a limited number of relatively simple circuit elements rather than having to deal with an exponentially exploding multiplicity of functional [[State (computer science)|state]]s and state transitions. While the task of testing a single logic gate at a time sounds simple, there is an obstacle to overcome. For today’s highly complex designs, most gates are deeply embedded whereas the test equipment is only connected to the primary [[Input/output]]s (I/Os) and/or some physical test points. The embedded gates, hence, must be manipulated through intervening layers of logic. If the intervening logic contains state elements, then the issue of an exponentially exploding [[state space]] and state transition sequencing creates an [[Computational complexity theory|unsolvable problem]] for test generation. To simplify test generation, DFT addresses the accessibility problem by removing the need for complicated state transition sequences when trying to control and/or observe what’s happening at some internal circuit element.

Depending on the DFT choices made during circuit design/implementation, the generation of Structural tests for complex logic circuits can be more or less [[Automatic test pattern generation|automated]]. One key objective of DFT methodologies, hence, is to allow designers to make trade-offs between the amount and type of DFT and the cost/benefit (time, effort, quality) of the test generation task.

== Looking forward ==

One challenge for the industry is keeping up with the [[Moore's law|rapid advances in chip technology]] (I/O count/size/placement/spacing, I/O speed, internal circuit count/speed/power, thermal control, etc.) without being forced to continually upgrade the test equipment. Modern DFT techniques, hence, have to offer options that allow next generation chips and assemblies to be tested on existing test equipment and/or reduce the requirements/cost for new test equipment. At the same time, DFT has to make sure that test times stay within certain bounds dictated by the cost target for the products under test.