Memory controller: Difference between revisions

Revision as of 16:06, 13 June 2007

Revision as of 10:44, 19 July 2007

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==Dual-channel memory==

'''[[Dual Channel]]''' memory controllers are memory controllers where the DRAM devices are separated ontoon to two different bussesbuses to allow two memory controllers to access them in parallel. This doubles the theoretical amount of bandwidth of the bus. In theory, more channels can be built (a channel for every DRAM cell would be the ideal solution), but due to wire count, [[Crosstalk (electronics)|line capacitance]], and the need for parallel access lines to have identical lengths, more channels are very difficult to add.

==Fully buffered memory==