Design for testing: Difference between revisions

Revision as of 06:31, 3 August 2007

Revision as of 18:44, 19 October 2007

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== Looking forward ==

One challenge for the industry is keeping up with the [[Moore's law|rapid advances in chip technology]] (I/O count/size/placement/spacing, I/O speed, internal circuit count/speed/power, thermal control, etc.) without being forced to continually upgrade the test equipment. Modern DFT techniques, hence, have to offer options that allow next generation chips and assemblies to be tested on existing test equipment and/or reduce the requirements/cost for new test equipment. AtAs thea same timeresult, DFT hastechniques are continually being updated, such as incorporation of compression, in order to make sure that testtester application times stay within certain bounds dictated by the cost target for the products under test.

== Diagnostics ==

Especially for advanced semiconductor technologies, it is expected some of the chips on each manufactured [[Wafer (electronics)|wafer]] contain defects that render them non-functional. The primary objective of testing is to find and separate those non-functional chips from the fully functional ones, meaning that one or more responses captured by the tester from a non-functional chip under test differ from the expected response. The percentage of chips that fail test, hence, should be closely related to the expected functional yield for that chip type. In reality, however, it is not uncommon that all chips of a new chip type arriving at the test floor for the first time fail (so called zero-yield situation). In that case, the chips have to go through a debug process that tries to identify the reason for the zero-yield situation. In other cases, the test fall-out (percentage of test fails) may be higher than expected/acceptable or fluctuate suddenly. Again, the chips have to be subjected to an analysis process to identify the reason for the excessive test fall-out.