Pulse transition detector: Difference between revisions

Revision as of 09:20, 2 October 2007

Revision as of 07:32, 9 November 2007

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{{Orphan|date=November 2006}}

A '''Pulse transition detector''' (PTD) is aused devicein comprisedflip offlops anin [[ANDorder gate]]to andachieve aedge [[NOTtrigerring gate]]in usedthe inciruit. It merely converts the clocks rising edge triggeredto a [[Flipvery flop]]snarrow pulse.

The PTD consists of a delay gate (which delays the clock signal) and the clock signal itself passed through a NAND gate and then inverted.

When a pulse reaches its input it sends a spike through the output, this spike causes the flip-flop to change state on the positive edge of the pulse

The benefit of edge trigerring is that it removes the problems of zeroes and ones catching associated with pulse trigerred flipflops (eg. master slave flip flops).

{{tech-stub}}

[[Category:Logic gates]]