Cell microprocessor implementations: Difference between revisions

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Revision as of 02:38, 13 December 2007

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The entry for 2.0  GHz operation at 0.9 V represents a low power configuration. Other entries show the peak stable operating frequency achieved with each voltage increment. As a general rule in CMOS circuits, power dissipation rises in a rough relationship to V^2 * F, the square of the voltage times the operating frequency.

Though the wattage measurements provided by the IBM authors lack precision they convey a good sense of the overall trend. These figures show the part is capable of running above 5  GHz under test lab conditions--though at a die temperature too hot for standard commercial configurations. The first Cell processors made commercially available were rated by IBM to run at 3.2  GHz, an operating speed where this chart suggests a SPU die temperature in a comfortable vicinity of 30 degrees.

Note that a single SPU represents 6% of the Cell processor's die area. The wattage figures given in the table above represent just a small portion of the overall power budget.

===Future editions in CMOS===

IBM has publicly announced their intention to implement Cell on a future technology below the 90 nm node to improve power consumption. Reduced power consumption could ''potentially'' allow the existing design to be boosted to 5  GHz or above without exceeding the thermal constraints of existing products.

====Prospects at 65 nm====

The most likely design node for a future Cell processor is the upcoming 65nm node in which IBM and Toshiba have already invested great sums of money. <!-- found scrap on the Inquirer that Sony and Tosh committed $190 m to achieve some advanced generation ahead of schedule but never reported back on progress, not worth referencing formally sooo it becomes "great [unsubstantiated] sums of money" --> All things remaining equal, a reduction to 65 nm would reduce the existing 230 mm² die based on the 90 nm process to half its current size, about 120 mm², greatly reducing IBM's manufacturing cost as well.

On 12th of March 2007, IBM announced that it started producing 65nm Cells in its East Fishkill fab. The chips produced there are apparently only for IBMs own Cell [[Computing_bladeComputing blade|blade]] servers, a timeframe for integration of these chips into the [[Playstation 3]] has not yet been announced.

IBMs news release is scarce on technical details. So far it is only known that these 65nm-Cells clock up to 6 &nbsp;GHz and run on 1.3V core voltage, as [http://news.spong.com/article/11413?cb=936 demonstrated] on the [[ISSCC]] 2007. This would give the chip a theoretical peak performance of 384 GLFOPS in single precision, a significant improvement to the 204.8 GFLOPS peak that a 90nm 3.2 &nbsp;GHz Cell could provide with 8 active SPUs. IBM further announced it implemented new power-saving features and a dual power supply for the SRAM array. Further improvements remain shady so far, but this version is not yet the rumoured "Cell+" with enhanced Double Precision floating point performance, which is still scheduled for 2008 according to the [http://www-5.ibm.com/at/symposium/pdf/00_Collaborative_Innovation_and_the_Cell_Broadband_Engine.pdf Roadmap].

So far this seems to be a pretty straighforwardstraightforward [[Die_Die (integrated_circuitintegrated circuit)|die]]-shrink, as the size of the Local Store RAM and number of SPUs remain the same. This chip should significantly reduce power consumption and be cheaper to produce thanks to the much smaller die-size.

IBM could elect to partially redesign the chip to take advantage of additional silicon area in future revisions. The Cell architecture already makes explicit provisions for the size of the local store to vary across implementations. A chip-level interface is available to the programmer to determine local store capacity, which is always an exact binary power.