Content deleted Content added
Line 2:
* many standard [[instruction set]] [[microprocessor]] [[Multi-core (computing)|cores]],
* integrated low-[[Latency (engineering)|latency]] [[memory controller]],
* hardware [[accelerator (computing)|acceleration]] features for [[packet (information technology)|packet]] handling. Manycore processors make better use of silicon real estate and have lower power requirements than monolithic sequential processors.
Current software architectures can scale on current [[Multi-core (computing)|multicore]] architectures to about eight processors but have poor ability to scale beyond that number.
With the introduction of multiple cores per processor '''manycore''' devices are generally considered to be processors with greater than eight cores.
Line 56:
=== Integrated memory controllers ===
Performance of typical MPU applications, such as [[packet (information technology)|packet]] processing and [[network control protocols]] (e.g. [[Signalling (telecommunications)|signalling]] and [[call control]]), is often sensitive to first-access [[memory latency]], i.e. the time taken to access memory that is not [[Cache|cached]] on chip, owing to high cache miss rate. This is sometimes more important than peak [[memory bandwidth]]. To achieve low first-access latency MPUs have integrated [[memory controllers]]. This is distinct from [[Intel]] and [[IBM]] general purpose processors that use separate memory controller devices adjacent to the processors and are more optimized for maximum bulk memory throughput.
=== Integrated streaming packet IO hardware ===
| |||