Memory controller: Difference between revisions

Revision as of 11:45, 16 December 2007

Revision as of 19:04, 8 January 2008

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Reading and writing to DRAM is facilitated by use of [[multiplexer]]s and [[demultiplexer]]s, by selecting the correct row and column address as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM can select the correct memory ___location and return the data (once again passed through a multiplexer to reduce the number of wires necessary to assemble the system).

Bus width is the measure of how many parallel lanes of traffic are available to communicate with the memory cell. Memory controllers bus width ranges from [[8-bit]] in earlier systems, to 256-bit systems in more complicated systems and video cards (typically implemented as four, [[64-bit]] simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a [[128-bit]] memory device).

==Double data rate memory==