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Bus width is the measure of how many parallel lanes of traffic are available to communicate with the memory cell. Memory controllers bus width ranges from [[8-bit]] in earlier systems, to 256-bit in more complicated systems and video cards (typically implemented as four, [[64-bit]] simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a [[128-bit]] memory device).
==Double data
'''Double Data Rate''' DDR memory controllers are used to drive [[DDR SDRAM]], where data is transferred on the rising and falling access of the memory clock of the system. DDR memory controllers are significantly more complicated than Single Data Rate controllers, but allow for twice the data to be transferred without increasing the clock rate or increasing the bus width to the memory cell.
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