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In [[computer architecture]], a '''systolic array''' is a pipe network arrangement of [[data processing unit]]s ([[DPU]])s (see figure, for instance, with 32 bit wide DPUs). DPUs are similar to [[central processing unit]]s ([[CPU]])s, but do not have a [[program counter]], since operation is transport-triggered, i.e., by the arrival of a data object (also used in [[transport triggered architecture]]s), in an [[array]] (often rectangular) where data flows across the array between neighbour DPUs, often with different data flowing in different directions. The [[data stream]]s entering and leaving the ports of the array are generated by [[auto-sequencing memory]] units (ASMs). Each ASM includes a [[data counter]]. In [[Embedded System]]s a data stream may also be input from and/or output to an external source.
[[image:systolic_array.jpg|thumb|240px]]
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